Clock Buffer-Distributor Required

Hi Hari,

Most of our clock buffer devices do not have tri-state outputs. Instead, many of our clock buffers have an output enable feature which can be used to drive the output to a logic low state if the enable pin is pulled low.

CDC351 has tri-state outputs, but it is a 1:10 buffer and operates from a 3V supply.
Other 1:2 buffers that may work are CDCLVC1102, CDCLVP1102, CDCLVP2102, or CDC3RL02. These device have output enable and can operate from a 2.5V supply.

Kind regards,
Lane

Hi Hari,

CDC351 is a 1:10 fanout buffer while the SN74 part is a dual channel buffer.
In general, if you need to buffer high speed, low jitter clocks, then pick clock buffer. For low speed clocks, usually jitter is not a concern, then pick logic buffer.

Hi Hari,

Yes, I think so.

Hi Hari,

Right, the datasheet did not specify the acceptable clock frequency clearly, I apologize for this.
There is a plot in section 9.2.3 that shown the current consumption vs frequency. From here, we can see that this device can support more than 60MHz clock.

Hi Hari,

Input transition rate specified the slowest acceptable slew rate. That is, the slew rate can be 2ns/V but not 22ns/V.

Hi Hari,

I am afraid there is no rise and fall time spec in the datasheet.

Hi Hari,

These specifications are usually explicit in the datasheet and one cannot easily relate one of these parameters to the other.

Regards
Arvind Sridhar