Data capture using 500 MSPS parallel LVDS ADC and DAC

vinitk99

I am looking for FPGA board for 500 MSPS parallel LVDS ADC(ADS5463) and DAC(DAC3152) interface. I am looking at ZC706 as one of the options but not sure yet.

The data read window for the ADC is around 800 ps (before jitter/uncertainty, signal integrity, board routing skew etc...).

If I plan to use ZC706 as my FPGA board,

What are the precautions I need to take if I plan to design and implement this system in Vivado(Xilinx based software)?

What are the possible pitfalls for this implementation?

What are the other options that I should be looking at I want to implement this design successfully?

Thank you,

over 5 years ago

0 Yusuf%20Agoro over 5 years ago

TI__Expert 4880 points

Hey VK,

I submitted your question to a device expert and they should be with you as soon as they can.

thanks

Yusuf

0 vinitk99 over 5 years ago in reply to Yusuf%20Agoro

Intellectual 280 points

Thank you Yusuf.

0 Neeraj Gill over 5 years ago

TI__Mastermind 20541 points

Hi VK,

Here is the link to the TI design which would answer most of your questions. www.ti.com/.../TIDA-00069

Regards,
Neeraj

0 vinitk99 over 5 years ago in reply to Neeraj Gill

Intellectual 280 points

Thank you Neeraj.

-VK

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Data capture using 500 MSPS parallel LVDS ADC and DAC