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LMK01010: Single-ended Sine Wave Input, 10 output clock buffer

Part Number: LMK01010
Other Parts Discussed in Thread: LMK00301

Is there an equivalent of LMK01010 with 10 outputs?

Thank you

  • See LMK00301. It is a very low-jitter 1:10 differential clock buffer but without divider capability.

  • Alan,

    Since the LMK00301 datasheet does not specify the single-end sine wave operation of CLKin, may you clarify if the following features are supported:

    1) Can both CLKin0 and CLKin1 be driven by single-ended sine wave up to frequency 700 MHz?
    2) What is the power requirement for the sine wave signal for single-ended operation at 700 MHz?
    3) Is the termination for single-ended sine wave input the same as Figure 12 in the LMK01010 datasheet?
    3) What is the LVDS additive jitter with CLKin0 and CLKin1 driven by single-ended sine wave at ~700 MHz(12 kHz to 20 MHz)?

    I appreciate your continuous support.

  • 1. Yes.
    2. Input power should between +8 to +10 dBm. This should give optimal additive jitter by having input slew rate >= 3 V/ns.
    3. Source --> 50-ohm trace --> 0.1uF AC-coupling cap --> 50-ohms termination from CLKinX_P and CLKinX_N. CLKinX_N should also have 0.1uF cap to GND. The 50-ohm termination across the P and N inputs will ensure both inputs are biased (internally) to the same voltage.
    4. Additive jitter should be less than 40 fs RMS (assumes input slew rate >= 3 V/ns).