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LMX2594: Doubt in the -236dBc/Hz noise floor (realistic value around -228dBc)

Part Number: LMX2594
Other Parts Discussed in Thread: TIDA-01346

Dear TI,

the issue if the LMX2594 has a noise floor of -236dBc/Hz has been raised once before. The answer from TI and the datasheet itself proving the -236dBc value is not clear though.

The noise floor value in question of -236dBc/Hz is proven only from the Figure 14 - "Calculation of PLL Noise Metrics" in the datasheet. However, the noise floor itself is not shown in the measurement trace in this Figure at all! What is shown is the 1/f noise and not the flat phase noise region. You may draw the red line as an indication of the flat region, but this red line without the measurement data trace is misleading.

Calculating the true noise floor of the part LMX2594 can be done from the several phase noise measurements in the datasheet, the eval board and other LMX2594-related gizmos (i.e. TIDA-01346, Multiple PLL Combination Reference Design).

Calculating the PLL noise floors and therefore FOMs from the Figures 3, 4, 5, 6, 7 and 9 (hopefully TI used Wenzel 100MHz OCXO for these figures) using the 20LOG(N) and 10LOG(Fpd) reveals the realistic value of -228dBc/Hz, 8dB worse than the specified value of -236dBc:

Fig. 3: Flat noise floor at 100kHz offset: -107.5dBc/Hz - 20*LOG(15000/200) - 10*LOG(200e6) = -228.0dBc/Hz!

Please clarify the issue or the possible miscalculation.

Thanks and best regards,


  • Leon,

    The key here is that one has to properly isolate the PLL figure of merit from the VCO phase noise and PLL 1/f noise and these figures you mention do not do that.

    To measure the true figure of merit, you need an adequate reference, account for the PLL 1/f noise (treated independently of figure of merit), and have a sufficiently wide loop bandwidth to ensure that you are really measuring the PLL noise and not the VCO noise.
    Sometimes, the VCO noise can crop inside the loop bandwidth and this noise appears to be flat and mistaken for PLL noise.

    So to properly measure the PLL figure of merit, you make the loop bandwidth as wide as possible and choose a very low phase margin.
    Figures 3,4,5,6,7, and 9 do NOT have wide enough loop bandwidth. These are not for demonstrating the PLL figure of merit, but rather for showing optimal jitter. But for optimal jitter, the VCO will contribute to in-band phase noise.

    The -129/-236 numbers were derived by a best curve fit. Yes, it would be nice to make a 5-10 MHz loop bandwidth so we could clearly show the true noise floor so it could be easy to directly measure the PLL figure of merit away from the PLL 1/f noise and VCO noise, but I could only get on the order of 1-2 MHz, so these numbers need to be extrapolated. I guess one could put an active filter to allow one to isolate the VCO input capacitance and get a sufficiently wide loop bandwidth, but we didn't do this.

    So in summary, the figtures you mention do not directly show the PLL figure of merit.

    Now this might be the question is what good is to have -236 dBc/Hz figure of merit if there is now way to see it inside the loop bandwidth of the PLL? Isn't that sort of having the power to turn invisible, but only when nobody looks at you? But there is value. The PLL figure of merit adds to the PLL 1/f noise and although is hard to directly see, the impact can be seen on closer offsets. Also, outside the loop bandwidth, the PLL noise can also contribute and the PLL noise can contribute far outside the loop bandwidth of the PLL, and here, the PLL figure of merit might dominate. If you were to put -228 number for figure of merit to the PLLatinum Sim and to simulate these plots in the datasheet, you would find the simulations would be way pessimistic and also the flat portion of the PLL noise would be much higher than the plot, as this flat portion of the curve has a significant VCO phase noise contribution.