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LMK62A2-200M: What is slew rate in LVDS mode?

Part Number: LMK62A2-200M
Other Parts Discussed in Thread: LMK00306

I'm using the LMK62A2-200M in a product design to drive the LMK00306.  The LMK00306 says the clock inputs require a driving clock signal with a 3V/ns slew rate (section 9.1).  In the datasheet for the LMK62A2-200M section 6.8 it says HCSL outputs have a slew rate from 1V/ns to 3V/ns, but it says nothing about LVDS.  I need to drive an LVDS clock from LMK62A2-200M to the LMK00306.  How do I know if the LVDS output from the LMK62A2-200M won't cause excessive phase noise?

Thanks!

  • LVDS will have differential output slew rate of ~1.8 V/ns typ, which I computed from differential output pk-pk swing and output rise/fall time specs). Based on this, I used Figure 10 phase noise floor vs. input slew rate at 156.25 MHz (closest frequency to 200 MHz) to estimate the noise floor to be around -153.6 dBc/Hz (after subtracting the Source noise contribution to the LVDS noise curve). Integrating this phase noise value over a 12 kHz to 20 MHz jitter integration bandwidth, I estimate it would could add about 105 fs RMS phase jitter to your LMK62A2-200M oscillator. Since the LMK oscillator has 150 fs RMS phase jitter, you could expect the overall phase jitter to be around 183 fs RMS (= SQRT(105^2 + 150^2)).

    Alan