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LMK00101: Differential or Single Ended Clock Distribution

SM
Expert 1730 points
Part Number: LMK00101
Other Parts Discussed in Thread: LMK00301, LMK04808, LMK01010, LMK01020

Hello,

     We are in the process of designing a multi-channel data acquisition system. The ADCs will be spread across several (8 at the moment) daughter boards while the reference clock will be generated on the mother board.  The ADCs in use have a single ended clock input and the clock will be generated by a OCXO. 

There are two options of distributing the clock to the daughter boards 

Option 1: Convert the single ended output (from OCXO) to differential using a clock distribution chip, route the different outputs as differential signals across the motherboard and convert them back to single ended using appropriate converters. 

Option 2: Using a clock single ended clock distribution chip route the different outputs as single ended signals across the motherboard and feed them directly to the converters. 

The problem is as follows:

Clock skew has to be minimized across each daughter board so that the conversion can take place in a synchronous manner. The LMK00101 has very low clock skew and seems to be an ideal choice. 

However we do not know the impact of routing single ended clocks across a motherboard (noise getting coupled to the clock). 

The theoretical solution is to differential signalling (Eg. LMK00301). The first shortfall is the output skew which is higher for the LMK00301. The other problem with this approach is the use of another device that will convert the differential clock to single ended at the converter. The part to part skew of such a device is very high and not to mention the additive jitter contributed. In other words the differential signalling adds more additive jitter while protecting the clock along the way and complicating the synchronization process. 

These converters will be interfaced to an FPGA so a narrow bandwidth solution to the problem is to compensate for the clock skew by delaying the digitized signals in the FPGA but the wide bandwidth problem remains. 

Further: Clock skew is independent of the clock frequency so in order to achieve better synchronization would it be smarter to use a lower frequency clock (the converters have in-built PLLs to generate the desired clock)? 

Looking forward to your inputs and thank you for your time,

  • 0
    TI__Mastermind 28540 points

    Hello,

    SM said:
    The ADCs in use have a single ended clock input and the clock will be generated by a OCXO. 

    What is the frequency used by the ADCs?

    SM said:
    There are two options of distributing the clock to the daughter boards 

    I like the first option of keeping CMOS to keep simplicity, however...

    If you do choose to convert to differential and are worried about increased skew in the system, you might consider a device such as the LMK01010 or LMK01020 for fanout of 8 clocks with the ability to apply analog delay adjust in 150 ps steps.  The LMK04808 has the ability to run in distribution mode and apply analog delay adjust in 25 ps, but while the LMK04808 has 12 CLKouts, they are in 6 pairs, and in each pair there is only one analog delay which each output of the pair may choose to use or bypass.  Another consequence of analog delay is increased analog delay variation over temperature and when using analog delay, turning the analog delay block on does incur a time delay overhead if you were to have some outputs using analog delay and others not.  On LMK04808 it's about 500 ps.

    Another option to achieve adjustable output phase is to use digital delay, but this would require using the device (like LMK04808) with a PLL, this allows you to achieve a digital phase adjustment at half the VCO period.  So for 3 GHz VCO frequency, ~166.7 ps.  These adjustments may be too granular for your application... although digital delay and analog delay can be intermixed for finer delay steps relating to the size of analog delay step and digital delay step in a 'Vernier' fashion.

    SM said:
    However we do not know the impact of routing single ended clocks across a motherboard (noise getting coupled to the clock). 

    A single ended trace will cause more EMI and be more susceptible to EMI.  I've seen on an EVM crosstalk due to traces vary 10 to 30 dB depending aggressor single ended or diff, and victim single ended or diff.  Proximity of traces is also a large variance to crosstalk performance, but differential to differential will provide the best immunity while single ended to single ended the worst.

    SM said:
    Further: Clock skew is independent of the clock frequency so in order to achieve better synchronization would it be smarter to use a lower frequency clock (the converters have in-built PLLs to generate the desired clock)? 

    Not necessarily.  An PLL will have skew variation from reference to feedback and this will also shift over temperature.

    I expect the minimum skew will be to run with a minimum number of components, which in your case is single ended fanout if you can tolerate the EMI both ways.

    One final note, if the output from OCXO is sine wave, be aware of the slew rate of the output signal, this may be important for low frequency (like 10 MHz) sine waves.

    Hope this helps.

    73,
    Timothy

  • 0 in reply to Timothy T
    Expert 1730 points
    Thanks a lot for the insightful answer!