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Original question:

LMK04828: No outputs

LMK04828: No outputs

Cindy Wei
Prodigy 290 points
Part Number: LMK04828


I was able to get stable clock output with 800MHz input, but shaking clock output or nothing with 640MHz input.  LMK is powered up at 3.3V with current measured at 4400mA (power down=0.96mA).  Below is lmk programming.

void LMK::lmkspi_TICS_Pro()

{

SPI::wspi_lmk(0x0000, 0x90);

SPI::wspi_lmk(0x0000, 0x00);

SPI::wspi_lmk(0x0002, 0x00);

SPI::wspi_lmk(0x0003, 0x06);

SPI::wspi_lmk(0x0004, 0xD0);

SPI::wspi_lmk(0x0005, 0x5B);

SPI::wspi_lmk(0x0006, 0x00);

SPI::wspi_lmk(0x000C, 0x51);

SPI::wspi_lmk(0x000D, 0x04);

SPI::wspi_lmk(0x0100, 0x64);//DCLKOUT0 divider=4

SPI::wspi_lmk(0x0101, 0x44);

SPI::wspi_lmk(0x0102, 0x55);

SPI::wspi_lmk(0x0103, 0x00);//02);

SPI::wspi_lmk(0x0104, 0x20);//22);

SPI::wspi_lmk(0x0105, 0x00);

SPI::wspi_lmk(0x0106, 0xF0);

SPI::wspi_lmk(0x0107, 0x11);

SPI::wspi_lmk(0x0108, 0x01);//0C);

SPI::wspi_lmk(0x0109, 0x55);

SPI::wspi_lmk(0x010A, 0x55);

SPI::wspi_lmk(0x010B, 0x00);

SPI::wspi_lmk(0x010C, 0x20);//22);

SPI::wspi_lmk(0x010D, 0x00);

SPI::wspi_lmk(0x010E, 0xF0);

SPI::wspi_lmk(0x010F, 0x60);

SPI::wspi_lmk(0x0110, 0x64);//DCLKOUT4 divider=4

SPI::wspi_lmk(0x0111, 0x44);

SPI::wspi_lmk(0x0112, 0x55);

SPI::wspi_lmk(0x0113, 0x00);//01);

SPI::wspi_lmk(0x0114, 0x00);//02);

SPI::wspi_lmk(0x0115, 0x00);

SPI::wspi_lmk(0x0116, 0xF1);

SPI::wspi_lmk(0x0117, 0x16);//CWEI: DCLKOUT4=LVPECL20=0x16; LVDS=0x11

SPI::wspi_lmk(0x0118, 0x64);//DCLKOUT6 divider=4

SPI::wspi_lmk(0x0119, 0x55);

SPI::wspi_lmk(0x011A, 0x55);

SPI::wspi_lmk(0x011B, 0x00);

SPI::wspi_lmk(0x011C, 0x00);//02);

SPI::wspi_lmk(0x011D, 0x00);

SPI::wspi_lmk(0x011E, 0xF1);

SPI::wspi_lmk(0x011F, 0x06);//CWEI: DCLKOUT6=LVPECL20=0x06; LVDS=0x01

SPI::wspi_lmk(0x0120, 0x08);

SPI::wspi_lmk(0x0121, 0x55);

SPI::wspi_lmk(0x0122, 0x55);

SPI::wspi_lmk(0x0123, 0x00);

SPI::wspi_lmk(0x0124, 0x20);//22);

SPI::wspi_lmk(0x0125, 0x00);

SPI::wspi_lmk(0x0126, 0xF0);//F8);

SPI::wspi_lmk(0x0127, 0x60);

SPI::wspi_lmk(0x0128, 0x08);

SPI::wspi_lmk(0x0129, 0x55);

SPI::wspi_lmk(0x012A, 0x55);

SPI::wspi_lmk(0x012B, 0x00);

SPI::wspi_lmk(0x012C, 0x00);//02);

SPI::wspi_lmk(0x012D, 0x00);

SPI::wspi_lmk(0x012E, 0xF9);

SPI::wspi_lmk(0x012F, 0x00);

SPI::wspi_lmk(0x0130, 0x64);//DCLKOUT12 divider=4

SPI::wspi_lmk(0x0131, 0x55);

SPI::wspi_lmk(0x0132, 0x55);

SPI::wspi_lmk(0x0133, 0x00);

SPI::wspi_lmk(0x0134, 0x20);//22);

SPI::wspi_lmk(0x0135, 0x00);

SPI::wspi_lmk(0x0136, 0xF0);

SPI::wspi_lmk(0x0137, 0x11);

SPI::wspi_lmk(0x0138, 0x40);

SPI::wspi_lmk(0x0139, 0x03);

SPI::wspi_lmk(0x013A, 0x00);//SYSREF div by 480=0x13A(0x01)+0x13B(0xE0)

SPI::wspi_lmk(0x013B, 0xA0);//SYSREF div by 160=0x13A(0x00)+0x13B(0xA0)

SPI::wspi_lmk(0x013C, 0x00);

SPI::wspi_lmk(0x013D, 0x08);

SPI::wspi_lmk(0x013E, 0x03);

SPI::wspi_lmk(0x013F, 0x07);

SPI::wspi_lmk(0x0140, 0xF3);//F1);

SPI::wspi_lmk(0x0141, 0x00);

SPI::wspi_lmk(0x0142, 0x00);

SPI::wspi_lmk(0x0143, 0x10);

SPI::wspi_lmk(0x0144, 0xFF); //7F);

SPI::wspi_lmk(0x0145, 0x7F);

SPI::wspi_lmk(0x0146, 0x00);

SPI::wspi_lmk(0x0147, 0x13);

SPI::wspi_lmk(0x0148, 0x02);

SPI::wspi_lmk(0x0149, 0x42);

SPI::wspi_lmk(0x014A, 0x02);

SPI::wspi_lmk(0x014B, 0x02);

SPI::wspi_lmk(0x014C, 0x00);

SPI::wspi_lmk(0x014D, 0x00);

SPI::wspi_lmk(0x014E, 0xC0);

SPI::wspi_lmk(0x014F, 0x7F);

SPI::wspi_lmk(0x0150, 0x00);

SPI::wspi_lmk(0x0151, 0x02);

SPI::wspi_lmk(0x0152, 0x00);

SPI::wspi_lmk(0x0153, 0x00);

SPI::wspi_lmk(0x0154, 0x78);

SPI::wspi_lmk(0x0155, 0x00);

SPI::wspi_lmk(0x0156, 0x78);

SPI::wspi_lmk(0x0157, 0x00);

SPI::wspi_lmk(0x0158, 0x96);

SPI::wspi_lmk(0x0159, 0x00);

SPI::wspi_lmk(0x015A, 0x01);

SPI::wspi_lmk(0x015B, 0xD4);

SPI::wspi_lmk(0x015C, 0x20);

SPI::wspi_lmk(0x015D, 0x00);

SPI::wspi_lmk(0x015E, 0x00);

SPI::wspi_lmk(0x015F, 0x0B);

SPI::wspi_lmk(0x0160, 0x00);

SPI::wspi_lmk(0x0161, 0x01);

SPI::wspi_lmk(0x0162, 0x44);

SPI::wspi_lmk(0x0163, 0x00);

SPI::wspi_lmk(0x0164, 0x00);

SPI::wspi_lmk(0x0165, 0x0C);

SPI::wspi_lmk(0x0171, 0xAA);

SPI::wspi_lmk(0x0172, 0x02);

SPI::wspi_lmk(0x017C, 0x15);

SPI::wspi_lmk(0x017D, 0x33);

SPI::wspi_lmk(0x0166, 0x00);

SPI::wspi_lmk(0x0167, 0x00);

SPI::wspi_lmk(0x0168, 0x04);

SPI::wspi_lmk(0x0169, 0x59);

SPI::wspi_lmk(0x016A, 0x20);

SPI::wspi_lmk(0x016B, 0x00);

SPI::wspi_lmk(0x016C, 0x00);

SPI::wspi_lmk(0x016D, 0x00);

SPI::wspi_lmk(0x016E, 0x13);

SPI::wspi_lmk(0x0173, 0x60);

SPI::wspi_lmk(0x1FFD, 0x00);

SPI::wspi_lmk(0x1FFE, 0x00);

SPI::wspi_lmk(0x1FFF, 0x53);

}

  • 0
    TI__Prodigy 290 points
    Correction: LMK power up current is 400mA.
  • 0
    TI__Prodigy 290 points
    Output clock is shaking more as input frequency goes down. At input=400MHz, output clock seems not locked. To get a stable output clock, what is the input clock frequency range?
  • 0 in reply to Cindy Wei
    TI__Mastermind 28560 points
    Looks like you are using the device in distribution mode and providing a clock to CLKin1 and distributing it through the device.

    It appears your issue is that you are using continuous SYSREF. That will cause a continuous stream of SYSREF clocks which will also reset the dividers. I expect this is the reason for your troubles. For a quick test, program all SYNC_DIS# bits to 1.

    Please refer to datasheet section 9.3.2.1.1 for an example of programming to get JESD204B system going. Note step #3.

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Prodigy 290 points
    Timothy,

    Thanks for your reply. The question is why SYSREF is stable at 800MHz but jittery at 600MHz. Both are using continuous SYSREF. I will try your SYNC_DIS# bits tomorrow.

    Thanks,
    Cindy
  • 0 in reply to Cindy Wei
    TI__Mastermind 28560 points
    Hello Cindy,

    The SYSREF single is generated by the SYSREF divider. The SYSREF signal is able to reset itself. This could lead to a stable SYSREF for some frequencies based on some periodic relationship with the pipeline time it takes to reset the divider. At least that's my conjecture of what you saw.

    When you say stable output at 800 MHz, did you confirm you were getting a 5 MHz 50% duty cycle signal from your SYSREF outputs?

    I like to call what I think is going on, 'SYNCing yourself in the foot'. Let me know what happens, note there is a SYNC_DISSYSREF bit also.

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Prodigy 290 points

    At input=800MHz,

    * reg0x144=0xFF, output at SDCLKOUT3 is stable 5MHz 50% duty cycle

    * reg0x144=0x80, output at SDCLKOUT3 is stable 5MHz 50% duty cycle

    * reg0x144=0x7F, output at SDCLKOUT3 is stable 66.7MHz 50% duty cycle

    At input=752MHz,

    * reg0x144=0xFF, output at SDCLKOUT3 is jittery 4.7MHz 50% duty cycle (see attached video)

    * reg0x144=0x80, output at SDCLKOUT3 is same as above.

    * reg0x144=0x7F, output at SDCLKOUT3 is jittery 1GHz~2GHz

    At input<736MHz, for examle 640MHz,

    * reg0x144=0xFF, no output at SDCLKOUT3 on board#1. (Note on board#2, it is jittery 5MHz 50% duty cycle.  Below result are on board#1.)

    * reg0x144=0x80, no output

    * reg0x144=0x7F, no output

  • 0 in reply to Cindy Wei
    TI__Mastermind 28560 points
    Hello Cindy,

    The fact that things are now working at 800 MHz suggests to me that there could be some single strength issue.

    I would confirm the good signal integrity and termination of the CLKin1 path.

    73,
    Timothy