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CDC3S04: Phase Noise increase through clock buffer

PETER LUDLOW98
Prodigy 100 points
Part Number: CDC3S04
Other Parts Discussed in Thread: LMK01000

I'm using the CDC3S04YFFR to buffer a TCXO signal at 40 MHz (https://www.mouser.co.uk/datasheet/2/741/LFTCXO075801Cutt-1128696.pdf). I've measured the phase noise pre-buffer / post-buffer using a R&S FSW signal analyser and have found that it is being degraded by 10-16 dB for carrier offsets between 1 KHz and 1 MHz (see attached plot). However according to the datasheet the additive phase noise (specified at 38.4 MHz) is < -135 dBc/Hz across these offsets. 

I've attached a screenshot of my schematic - I did try adding more decoupling caps (1 uF/10 uF) at VDD_ANA (pin B3) but made no difference. Do you have any other suggestions?

  • 0
    TI__Mastermind 27911 points
    Peter,

    I haven't worked with this buffer, but have used some others like the LMK01000 series.
    The FSWP is a nice box, so I think it is a pretty trustworthy instrument.

    If the noise floor of the buffer is -135 and your input signal is about -142, then I would expect to see noise floor at 10*log(10^(-135/10) + 10^(-142/10)) = -134.2, but you look closer to -128, which is a good 6 dB off

    One thing I would check is the input slew rate of the buffer as a slower edge rate can sometimes translate into worse phase noise. Also, if this is differential input, then single vs/ differential might make a difference.

    Regards,
    Dean