Hello Ti experts,
I have a customer request concerning the programmable delays as documented in the LMK01020 data-sheet page 13 chapter "CLKoutX_DLY[3:0] -- Clock Output Delays "
These delays have on page 6 a statement that the "Maximum Allowable Delay" is 2250 ps, but no typical or minimal values are stated. There is as well a remark: "Specification is guaranteed by characterization and is not tested in production." in the data-sheet
Now my question: Is a delay variation of 5% to 10% reasonable for this chip?