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LMX2492: LMX2492 low reference frequency(10MHZ) locking and phase noise problem

Part Number: LMX2492

We have an issue with lmx2492:

We used to install 25MHz reference oscillators on our boards. With doubling reference frequency to 50MHz we obtained good phase noise.

Problems started when there was a need to use external reference frequency 10MHz.

In first experiments we used quartz crystal filter and transistor amplifier to filter and amplify reference frequency.  With internal frequency doubling we didnt see even pll lock.

When we programmed chip without frequency doubler, we seen lock but phase noise performance was terrible(10dB lower than calculated and spurs). Reference level on input was 5dBm.

Then we installed smidt trigger on reference path. We even obtained pll locking with reference frequency doubling. Noise performance was perfect, but when we connected boards in working construction performance degraded by 7dB in loop and we seen many spur noise. On shmidt trigger output we see oscillation with 3V level and 40-60% duty cycle. Chip reference input is AC coupled and loaded by 220Ohm.

Problem is that we dont see any connection between pll behavior and reference oscillation level and its duty cycle.

Did anyone tested chips with 10MHz reference frequency(with or without doubling)?

What is optimal reference path for system with external reference with input reference level +-5dBm?

What is predicted phase noise performance with reference frequency 10MHz with phase noise -150dBc/Hz on 1kHz offset(with and without doubling)?

  • jwizard,

    We do test this at 10 MHz, however there are some considerations at this low frequency.

    1. Low slew rate. If the slew rate is low, then the phase noise will degrade. For a sine wave, the zero crossing slew rate of A*sin(f*t) = A*f, so slew rate is proportional to frequency. Using a square wave should fix this issue.

    2. Harmonics. If you see the PLL mislocking to a higher frequency, it could be harmonics. Now proper harmonics for a square wave are good. However, if you have a high second harmonic, the PLL might try to lock to this. Sensitivity is better at 20 MHz than 10 MHz and if there is an AC coupling cap, it might have some impact there too.

    In any case, be aware of slew rate and harmonics for lower frequency signals, but a square wave is the best approach.

    As for the phase noise, PLLatinum Sim can predict this. I don't know your VCO freq, but if we assume 10 GHz, you should get about = -90 dBc/Hz @ 1 kHz with and without the doubler. This is on the 1/f noise portion of the PLL curve.

    However, likely your input reference is not clean enough to see the -90 dBc/Hz. If you take your input reference noise at 1 kHz and add 20*log(10 GHz/10MHz) = 60 dB to the 1 kHz noise, then this is what the PLL sees. In other words, if your 10 MHz input reference is -150 dBc/Hz @ 1 kHz offset , then this is -90 dBc/Hz @ 10 GHz. We would add this to the PLL noise and get -147 dBc/Hz as the sum of the two.

    Regards,
    Dean