LMK05028: 10MHz Output from 10MHz OR 1PPS Input

It is not possible to support a 1 Hz input and 10 MHz input simultaneously, since the DPLL R-dividers are 16-bit deep (max divide = 65536) so it cannot divide a 10-MHz input down to a common frequency of 1 Hz.   To avoid the script error, change all input frequencies to 1 (Hz), or change the input's DPLL assignment to "Unused".

Please try the attached tcs file which has the following attributes:

1. PLL1 is used to generate all 10 MHz outputs.  PLL2 is powered down.
2. 1 Hz input on REF IN0 assigned to DPLL1, and selected by register control.  Other inputs (IN1 to IN3) are set to Unused and Ignored.
3. DPLL1 in 3-loop mode with DPLL1 BW = 20 mHz and TCXO BW = 200 Hz.
4. VCO1 freq was forced to 4840 MHz in STEP 5 (from 4800 MHz to allow APLL1 to be in Fractional mode, since the XO frequency is 48 MHz).
5. 1-PPS input phase valid detector is enabled and set to max (6300 ns).  If your 1-PPS input has large wander (>6.3 us cycle-to-cycle variation), then you may need to disable the 1-PPS input detector.
6. DPLL1 lock detect threshold = 50 ppm, unlock detect threshold = 55 ppm
7. STATUS0/1 and GPIO5/6 pins are configured to output the following signals for DPLL lock behavior:
   1. STATUS0 = DPLL1 RDIV reference clock div-by-2 (i.e. 1-PPS input/2 ~ 0.5 Hz)
   2. STATUS1 = DPLL1 NDIV feedback clock div-by-2 (i.e. feedback to TDC ~ 0.5 Hz)
   3. GPIO5 = DPLL1 holdover active (should be 0 when 1-PPS input on REF IN0 is validated and selected)
   4. GPIO6 = DPLL1 loss of lock (should be 0 when DPLL1 frequency lock is detected)
   5. When phase-locked, you should see a stable phase relationship between the RDIV/2 and NDIV/2 signals on STATUS0/1, and GPIO5/6 are both 0.  You can also read-back the STATUS bits on the "Status & Interrupt" page.
   1. With 20 mHz DPLL BW, the DPLL will take a couple minutes to achieve lock.

LMK05028_3loop_Dpll1Bw=20mHz_Tcxo1Bw=200Hz_RefIn0=1pps_Tcxo=10M_Xo=48M0048_Out0to7=10M.tcs

Hope this helps! 

Alan

For the tcs files I sent, you do not need to "Update Frequency Plan" and do not need to "Run script" since I already did that already.  

When you load the tcs file and it writes all registers to the DUT, you only need to trigger a soft-reset to initialize the device blocks.  Upon reset, it will follow the device start-up sequence per the datasheet.

I'll respond to your latest update separately.

Alan

How much cycle-to-cycle timing variation do you have on your 1-PPS signal from GPS?

I am using a 1-PPS signal source from a Tek Arbitrary Waveform Generator (AFG, and am able to reliably achieve lock on both DPLLs after loading the tcs file, triggering a soft-reset, and waiting a couple minutes.  The DPLL lock was repeatable on each soft-reset event, and also after removing the 1-PPS input and reapplying it.

I suspect your 1-PPS signal could have large wander, which could be causing DPLL1 to have difficulty achieving reliable lock.  If the input is disqualified before DPLL1 achieves initial lock, then it could prevent DPLL1 from ever achieving lock ... in this case, you'd have to manually trigger a soft-reset to restart the startup / lock sequence.  Could you please try using a 1-PPS source from a stable Lab function generator (instead of from a GPS source)?

I will send an updated tcs file later that has the Interrupt bits configured and Interrupt flag output to one of the GPIO pins, so it can capture (latch) if the DPLL1 has detected a lost lock event, or if the input 1-PPS reference was lost (before DPLL1 achieves initial lock), or if DPLL1 has entered holdover (after DPLL1 achieved initial lock).  This could help you to troubleshoot the issue on your setup.

Alan