LMK04816: How to synchronize the output of two LMK04816 chips?

I tried the following methods:
1. Use power divider to connect input clock to CLKin1 (FBCLKin) and CLKin0. Use 0 delay mode, and choose FBCLKin as feed back. The result is that the output clock can be synchronized with the input clock steadily, and the phase difference between the output signal and the input signal is random after each power-on. Does this mean that feedback mode can't synchronize the two chips?
2. (Data Manual P31-P33) Both chips are in SYNC_POL_INV=1 state, waiting for SYNC PIN to output clock after high level. Using the same FPGA to send SYNC signals to two chips at the same time, the results are not ideal. Is the Distribution Path clock in the figure the internal VCO of the chip PLL2? Is this method feasible?