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CDCE72010: Power up issue

Jonathan Gamez
Prodigy 20 points
Part Number: CDCE72010

Hi,

I'm trying to set up a FFMC151 Mezzanine Card from Abaco.  This board contains a CDCE72010 chip and it's controlled form a FPGA.

As a first step, I just want to check that the CDCE is generating the clock signals according to the default configuration on the EEPROM, so I'm just switching the complete system on and using  the output 4 of the chip as a differential clock input for toggling an LED depending on a configurable counter value (at power on, the conter value is 0). The problem is that I cannot achieve a consistent behavior: some times the clock is generated as expected and the LED blinks fine when setting a proper counter value, and some times the LED is just blinking erratically at power on. The PD pin is tied to 1 and a pushbutton is used to control the RESET pin, but even resetting the chip doesn't help.

Are there any initialization steps that I'm missing?

  • 0
    TI__Mastermind 28530 points
    Hello Jonathan,

    I'm a bit confused on the situation -- Is it safe to assume there is no physical/hardware problem with this board/design as it is a produced board by Abaco and would have received testing upon product shipment? Wouldn't the EEPROM be set by Abaco for this product? Have you tried contacting Abaco for support?

    Having said that, and without knowing the default EEPROM which is giving you intermittent functionality. I think your root concern lies in the unexpected working and nonworking OUT4 behavior.

    * Can you confirm your procedure for loading from EEPROM?
    * Can you share the EEPROM programming?
    * What is your reference frequency and VCO frequency?
    * Can you measure the tuning voltage of the VCO in the working and nonworking case?
    * If you're able to probe the STATUS pin, As per page 36 of datasheet:
    > Can you program R12<bits 17, 18, 19, 20> = 1000. STATUS pin would confirm the reference selected. Ensure this is proper.
    > Can you program R12<bits 17, 18, 19, 20> = 0000. and R3<bit 0> = 0. The reference clock freq detector should show on the STATUS pin.

    73,
    Timothy
  • 0 in reply to Timothy T
    Prodigy 20 points

    Hi,

    It seems that my problem was that the EEPROM contents were not correctly loaded at power up. According to the datasheet, the SPI_LE signal has to be high at power up, and probably during this time the FPGA was configuring itself, failing to keep the proper value of the pin. The problem is solved by powering down and up the chip through the PD pin.

  • 0 in reply to Jonathan Gamez
    TI__Mastermind 28530 points
    Great! Thanks for sharing your finding, I appreciate it.

    73,
    Timothy