CDCE421A: How to program the CDCE421? Datasheet clarification

Hello Rishub,

"Repeat frequency of programming" appears to be the definition assigned to fSDATACLK which defines the useful constant 't' used the Table 5 for SDATA/CE timing requirements where t = 1/f_SDATACLK.  It seems a better name might have been bit rate frequency.

This one wire scheme appears to use a delayed version of rising edges of SDATA to sample the bit.  Visually it appears the delay is 0.5 t, which makes sense given the typical high/low durations of the pulse to achieve '0's or '1's into the device.  Where short high of 0.2 t followed by long low of 0.8 t will be sampled at 0.5 t as a 0.  Where as long high of 0.8 t followed by short low of 0.2 t will be sampled as a 1.  You can see this illustrated in figure 2.

I'm afraid I'm not aware of any code I can share for this.  However the EVM tool must have code implementing this.  Not sure if I could find this, and if I could I would have to go through a process to approve it for external release so this would not be a timely solution for you (if possible).

There may be good news for you.  I think that SPI could be used to execute this protocol.  Suppose your SPI is setup to burst 1 bit R/W + 7 bits address + 8 bits data.  If you look at only the data line you could...

Write b0111 1111 1111 1000 as high (write to address = 0x7F, data = 0xF8) and 

Write b0111 0000 0000 0000 as low (Address = 0x70, Data = 0x00).

To meet the timing with respect to the fSDATACLK parameter of typ 70 kHz.  You need a bit rate of 70 kHz * 15.  Because we needing to send 15 bits in this 1/70 kHz period.  70 kHz * 15 = 1050 kHz.  1 MHz SPI would meet the 60 to 80 kHz range for fSDATACLK.  The one bit delay of 0 for the R/W bit will be << 16 ms.

Take care of noting what happens with the DATA pin when between SPI transmissions, etc.

73,
Timothy

Hello Rishub,

9.841 µs seems close to me. Note that the bit period is nominally 1/70 kHz = ~14.3 µs. So 0.8 * 14.3 µs = ~11.43 µs is what you want target for your high signal pulse duration. Your measurement doesn't included the rise/fall time of either signal and your rise/fall times seem rather large.

If we assume a perfect square wave 0 ns rise/fall time with your info:
spi_bit_freq = 100 MHz / 96 = 0.96 µs
12 bits high time = 12 * 0.96 µs = 11.52 µs.

(theoretical high time - measured high time) / 2 = rise/fall time from 0% to 100%.
(11.52 µs - 9.841 µs) / 2 = 839.5 ns.

rise or fall time from 0% to 100% * 0.6 = rise or fall time from 20% to 80% = 503.7 ns.
> Your rise/fall time seems really long compared to nominal 2 ns.

It found it a bit odd that they showed units in ms instead of µs, since 'µs' appears to be the natural unit of time to use for this device given ~70 kHz. But really the unit is whatever unit 't' is in. Naturally you can scale this to suite you, so to specify a unit at all is a bit odd to me. The only absolute times given are the rise/fall times of 2 ns and the timeout time of 16 ms.

73,
Timothy