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Original question:

CDCLVD1216: CDCLVD1216 drive length

CDCLVD1216: Reflections on CDCLVD1216

Muni Pavan Kumar Reddy Kona
Prodigy 225 points
Part Number: CDCLVD1216

Hello,

I am using CDCLVD1216 to drive my TTL signal to fanout to 16 LVDS receivers.

But i am seeing a lot of reflections on LVDS output.

May i know the possible root cause. Can CDCLVD1216 drive 13" PCB microstrip line and 12 feet cable. Kindly let me know.

Thanks,

Muni

  • 0
    TI__Genius 16845 points

    Hi Muni,

    Yes, it can drive a 12 foot transmission line. I recommend to use the CDCLVD1216 IBIS model to simulate driving your transmission lines of desired length and plot the signal integrity. This is a way to determine whether the device can meet your requirements.

    It is recommended to design the output PCB traces with controlled differential impedance of 100 ohms to match the 100 ohm load termination. The 12 foot coax cable should be a matched pair with controlled impedance of 50ohms.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 225 points

    Hello Lane Boyd,

    Thanks for your response.

    Can I get the board file for "cdclvd1212evm".

    I would like to follow some guidelines for differential output traces. First revision board failed. We would like to correct the layout.


    Can I contact any application engineer in India for evaluation board support. Could you please direct me.

    Thanks,
    muni

  • 0 in reply to Muni Pavan Kumar Reddy Kona
    TI__Genius 16845 points

    Hi muni,

    Attached is the *.brd file. cco-evm-lvd1212-01.brd

    You may find these app notes helpful: 

    Some general PCB layout guidance for high speed traces:

    • Design the differential output trace as a 100-ohm controlled impedance pair. Alternatively, you could design them as 50-ohms single-ended traces, but route as a differential pair.
    • Unterminated stubs on these traces can degrade performance
    • Maintain a constant trace width to minimize impedance discontinuities
    • There should be a solid reference plane beneath the traces to minimize impedance discontinuities
    • Maintaining a clearance of three times the trace width on each side of the traces can improve isolation

    Do you have a local/regional FAE that you typically work with?

    Kind regards,
    Lane