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CDCE706: PLL synthesis Advice

Part Number: CDCE706

Dear,

We are planning to use this IC in our project ,as i am new towards the concept of the frequency synthesis i want of know the  basic working of the IC.

I have explored on the frequency synthesis but that i am not clear with the exact working.

it would be great if you help me in the understanding of the frequency synthesis of the IC.And also more importantly the working of the IC in generating the Frequency that synthesis in between 900 kHz to 1.1 Mhz.

So please suggest me some way in order to achieve the output and way to generate it.

It would be of great help that you could provide us some solution or any reference which could easily understood by the beginner in this topic.

Kind Regards,

Mit Shah

  • Hi Mit,

    CDCE706 uses a phase locked loop (PLL) to synthesize the output frequency. PLL theory is a complex topic, I can point you to some informational resources depending on your level of familiarity.

    To explain it simply, a PLL is a control system that uses feedback to synthesize an output that is phase locked to the input. This device uses a simple analog PLL consisting of phase detector, charge pump, loop filter, and integrated VCO. The VCO generates the feedback reference that is fed back to the phase detector for comparison to the input frequency. Output dividers are used to generate the output frequency as a fraction of the VCO frequency.

    You can program the device registers to configure the device. We have an EVM and companion software GUI available for purchase that can be used to simplify development.

    Kind regards,
    Lane

  • Hello Lane,

    Thank you for explaining PLL concept.

    But i am basically familiar with PLL concept,i am specifically confuse about the frequency synthesis.

    I need to design Ultrasound therapy device,in it piezo crystal needs frequency that varies between 0.9Mhz to 1.1 Mhz.

    So needed help on frequency synthesis.

    Thanks again.

    Regards,

    Mit shah

  • Hi Mit,

    If I understand correctly, you want to use the crystal as the input to CDCE706? Is that correct? In that case, what output frequencies do you need from CDCE706?

    I would like to help you better understand frequency synthesis, unfortunately I do not understand your question. Could you elaborate?

    Kind regards,
    Lane
  • Hi Lane,

    No the input crystal is stable i.e. 16Mhz.

    I need to generate output frequency variable like i said 900 khz to 1.1Mhz.

    The output frequency goes to piezo crystal that generates ultrasound waves.

    Every piezo crystals have different peak frequencies that varies near 1Mhz.

    So i need the output frequency variable.

    Regards,
    Mit shah
  • Hi Mit,

    Thanks for the information, I have a better understanding now. Interesting application.

    You would need to adjust the PLL settings to adjust the output frequency. The easiest way to accomplish it is to change the M, N, and P divider values; you can calculate the PLL output frequency using equation 1.

    One way to do it would be to set the VCO to 99MHz (N=99, M = 16). Then, change the P divider to set the output frequency: P = 110 produces 900kHz; P = 99 produces 1MHz; P = 90 produces 1.1MHz. In this case, the total set of output frequencies is 99Mhz / P, where P = 90, 91, 92, ... , 110.

    Another way to accomplish it would be to change the VCO frequency. In this instance, you may need to change the dividers as well, but it may allow more precise frequency control.

    Kind regards,
    Lane
  • Hi Lane,

    Thank you for the guidance you provided.

    I appreciate this.

    I have a better understanding now regarding the frequency synthesis.

    Regards,

    Mit