LMK04816BEVAL: Getting a 125 MHz Clock from the LMK04816 Eval Board

Hi Doug,

There is a way to use the 50 MHz reference input to generate 125 MHz and 6.25 MHz from PLL2, without modifications to the board. However, I will caution you that the solution without modifications is likely not what you want to do, because it does not fully take advantage of the jitter cleaner characteristics.

With no modifications, 50 MHz may be fed to either PLL1 with a phase detector frequency of the greatest common divisor of 50E6 and 122.88E6, which is 80 kHz. Likewise, the output 122.88 MHz can be fed to PLL2 with 80 kHz for the phase detector frequency (VCO = 2500 MHz); this is almost the GCD, but there is a Pre-N divider which prevents the use of 160 kHz. From there, with the N2 prescaler set to divide by 2, the output channels can be divided by 20 and 400 to achieve 125 MHz and 6.25 MHz respectively. However, pushing the phase detector frequency of PLL2 so low will result in higher PLL flat noise, so the total phase noise in this configuration would defeat the purpose of using a dual-loop jitter cleaner.

If the 50 MHz clock signal is high quality (low phase noise), it can be fed directly to the OSCin port, and the PLL2 phase detector frequency is simplified to 50 MHz (or 100 MHz if the reference input multiplier is used). This has the advantage of much lower PLL flat noise thanks to the higher phase detector frequency, but it bypasses PLL1 (and any potential for jitter cleaning). And if the 50 MHz input has substantial jitter, the reference noise will still dominate.

By substituting the on-board VCXO (122.88 MHz) with a pin-to-pin equivalent at a more friendly frequency (e.g. 100 MHz), many things become simplified. Now a "dirty" 50 MHz clock can be fed directly to PLL1, the jitter cleaner can maintain a frequency reference to the 50 MHz input while maintaining the much lower noise profile of the VCXO for the PLL2 reference input, and the clock outputs can be synthesized as in the case above. The on-board VCXO is a Crystek CVHD-950, and there are pin-to-pin models of the CVHD-950 available at 100 MHz.

For an in-depth analysis of PLL parameters and their interaction, take a look at the PLL Performance Simulation and Design Handbook. Also, the latest version of PLLatinum Sim software includes the LMK04816, which can be very helpful for visualizing the effect of different loop elements on the overall clock output behavior.

Regards,