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CDCM7005-SP: Clock Configuration

Part Number: CDCM7005-SP
  • Can we configure output clock as combination of 2 channel (2X2) LVCMOS and 3 channel LVPECL?
  • If configure as LVCOM , what will be the phase difference between Y0A and Y0B, means both clock will be  in phase or inverted clock?



Naveen Kumar HR

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