Other Parts Discussed in Thread: CODELOADER
I am trying to configure a LMK04816B Eval board device using TICs Pro. I am trying to generate 125 and 6.256 MHz clocks on the device. I have swapped out the 122.88 MHz VCXO (U2) with a 100 MHz version and I am driving CLKIn1 with 100 MHz (0.0 dBm).
I performed the following in TICS Pro and my Eval board:
- Load the default 122.88 MHz ClkIn1, 122.88 MHz VCXO
- Change the reference values on the PLL1 and PLL2 pages to 100 MHz
- Turn off EN_SYNC
- Modify the LD and HOLD Status pins to gather the following results:
PLL1_R/2 = 416.7 kHz
PLL1_N/2 = 416.7 kHz
PLL1 LD Locked
PLL2_R/2 = ~50 MHz
PLL2_N/2 = 56 MHz
PLL2 LD = Not Locked
(I noticed that the PLL2 VCO output was 2 GHz which TICs indicated was out of range for the PLL. I changed N Divider to 12 to place VCO at 2400 MHz)
PLL2_R/2 ~50 MHz
PLL2_N/2 47 MHz
PLL2 LD Not Locked
What do I need to do to lock the PLL2 at a frequency that derive 125 MHz and 6.25 MHz? Are there any other modifications that I need to do beside swap out the VCXO?
Thanks,
Doug