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CDCE949-Q1: operating mode

Aaron Spaete
Expert 4275 points
Part Number: CDCE949-Q1

Clocking team, 

I have a question regarding the CDCE949-Q1 clock synthesizers I2C bus specs.


1) How does the device determine if it is operating in Standard Mode or Fast Mode?

2) On page 5 of the datasheet (attached). The spec for the "SDA hold time" lists a MIN and MAX of 0 and 0.9 microseconds, respectively, for Fast Mode. How is the MIN zero and yet the standard mode MIN is also zero microseconds? Is there no defining boundary?

Thanks, 

Aaron

  • 0
    TI__Genius 12705 points

    Hello Aaron,

    The CDCE949-Q1 is operating in Slave mode on the I2C bus. The operating speed is determineed by the Master which controls the clock frequency.

    As the SDA is latched in at the falling edge of SCL, the minimum SDA hold time time is indeed 0.

    Please see figure 11 for an example timing diagram.

    Regards,