Other Parts Discussed in Thread: CDCI6214, , CDCE925
I need to generate four independent clock frequencies that can be programmed by a microcontroller in the range of 500kHz to 1MHz. This is for a lock-in style design, so the output is both the drive and reference and as long as an individual channel doesn't shift much over short time periods (milliseconds) it should not significantly impact the performance in my application if it drifts a bit over time or has low accuracy.
My plan is to take the output of the chip into a counter so as to scale the output frequency down if needed and also make the clock as close to a 50% symmetric duty cycle as possible, so the only load is the input to my counter chip that generates the real buffered output clock signal. These signals will all be in the 3.3V power domain.
I looked at a few other chips like the CDCI6214 but their datasheets were so complex I'm left without a clear understanding of what the best choice of chip would be here or if another clock synthesis approach would make more sense.
Is this CDCE906 chip the recommendation for such an application? My read is that I need to provide a 27MHz crystal and ensure the PLL produces at least 80MHz for the VCO, and then I can divide this down by any integer from 1-127 at the output and then feed my counter to drop it to the 500kHz-1MHz range, and I can mess around with the PLL divider ratio to shift the VCO base frequency if more precision is needed.
Does this mean that if I configure the N/M divider so that the PLL is running at 80MHz I can generate 2MHz, 1.860MHz, 1.739MHz, and 1.600MHz through a divide-by-2 counter to get reference clocks of 1MHz, 930kHz, 870kHz, and 800kHz? And then I can save this to EEPROM and leave it in memory to generate these frequencies until updated over I2C?
Thanks for the help, please let me know if you might recommend another part for this.
