Other Parts Discussed in Thread: LMK04805, LMK04808
I am trying to derive a 150 MHz and 125 MHz signal from a LMK04816 that is input with a 50 MHz reference clock.
When I run TICs Pro, it indicates that the PLL2 output is bounded from between 2370 MHz and 2600 MHz. Since I cannot find a common multiple for 125MHz and 150 MHz in the 2370-2600 range, I assume that I cannot derive these two clocks on the same part.
Am I wrong? How would I do this?
Regards,
Doug Bailey