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LMK04906: LMK04906: Dual PLL mode

Dilip Namdeo Mohol
Intellectual 1440 points
Part Number: LMK04906

 we are  using LMK04906 on Indus LC in Dual PLL, Internal VCO mode.

Could you please tell what will be the result if CLKIN0_[PN] is not enabled anytime after Power-on.

 

Originally this circuitry is intended for SyncE support.

But with current SW, SyncE is not enabled.

 

Hence I want to know if output clocks are guaranteed with CLKIN0_[PN] disabled.

 

 

LMK04906 register dump is captured below:

R0   0x00140280

R1   0x00140200

R2   0x00140200

R3   0x00140200

R4   0x00140200

R5   0x00140200

R6   0x04400000

R7   0x04400000

R8   0x04040000

R9   0x55555540

R10  0x91024100

R11  0x04011000

R12  0x1B8C0060

R13  0x03639060

R14  0x13700000

R15  0x80008000

R16  0xC1550400

R17  0x08002C80

R18  0x03200000

R19  0x99050000

R20  0x06000000

R21  0x00000800

R22  0x004F0000

R23  0x70000000

R24  0x000000C0

R25  0x02C9C400

R26  0xAFA80000

R27  0x1C003CC0

R28  0x00109C40

R29  0x008000A0

R30  0x050000A0

R31  0x59000D40

 

lmk04906.pdf

  • 0
    TI__Mastermind 29010 points

    Hello Dilip,

    If CLKin0 is never seen at any time after startup, the charge pump output of PLL1 will be held in tri-state. The VCXO driving PLL2 will likely have some frequency offset, which will propagate through PLL2 to the outputs.

    Currently, you do not have holdover mode enabled. Holdover mode programs a DC voltage on the output of the PLL1 charge pump when no input reference is detected. Holdover mode generally has higher frequency accuracy when signal is lost or not present at CLKin0. I recommend looking at datasheet section 8.3.5 for more information about programming holdover mode.

    Regards,