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CDCE62005: DAC3484EVM PLL_LOCK shows green, D1 is not lit...

Part Number: CDCE62005
Other Parts Discussed in Thread: LMK04828BEVM, DAC3484EVM,

I’m having trouble getting the CDCE62005 to lock and out a 131.072MHz FPGA clock output on the DAC3484EVM card.  The clock input is 153.6MHz LVPECL20 from an LMK04828BEVM connected to a balun to produce a single-ended input to the J9 connector.  The PLL won’t lock and the output drifts to 138.197MHz regardless of whether or not the 153.6MHz input click is connected or not.  I had this working 4 months ago, but now it seems the PLL won’t lock.

This morning it powered up, loaded, output the correct frequency, but the D1 Lock LED did not light.  Pressing the Wake Up button didn't seem to have an effect.  Could this PLL filter be temperature sensitive?  Below is the CDCE62005 VCO Settings through the DAC3484EVM Software Control GUI

   x00	   x0880
   x01	   x0100
   x02	   x8002
   x03	   xF001
   x04	   x4068
   x05	   x3E60
   x06	   x2900
   x07	   x0000
   x08	   x0000
   x09	   x8000
   x0A	   x0000
   x0B	   x0000
   x0C	   x0000
   x0D	   x0000
   x0E	   x0000
   x0F	   x0000
   x10	   x0000
   x11	   x0000
   x12	   x0000
   x13	   x0000
   x14	   x0000
   x15	   x0000
   x16	   x0000
   x17	   x0000
   x18	   x0007
   x19	   x0000
   x1A	   x0020
   x1B	   x0000
   x1C	   x0007
   x1D	   x0054
   x1E	   x0000
   x1F	   x0002
   x20	   x2400
   x22	   x1B1B
   x23	   x0000
   x24	   x0000
   x25	   x0000
   x26	   x0000
   x27	   x0000
   x28	   x0000
   x29	   x0000
   x2A	   x0000
   x2B	   x0000
   x2C	   x0000
   x2D	   x0000
   x2E	   x0000
   x2F	   x0000
   x30	   x0000
   x7F	   x0004
CDCE62005 Registers
Address	Data
00		68040320
01		68800301
02		83800302
03		EB040303
04		68860304
05		11280A55
06		440F3F76
07		3DF8FBC7
08		20009D98