CDCE949-Q1: Clock & timing forum

user3746678

Part Number: CDCE949-Q1

Hi,

In my design , CDCE949-Q1 input is a 25MHz cystal, the Y3 output is also 25MHz, which is used for Ethernet PHY. In datasheet, CDCE949-Q1 output clock jitter is Peak-to -Peak period jitter：

but the Ehternet PHY input clock jitter parameter is RMS phase jitter, which should be ＜3.0ps

so whether CDCE949-Q1 output phase jitter can meet this requierment? what's the phase jitter value of CDCE949-Q1 output clocks?

Thank you.

Regards.

Gavin

over 4 years ago

0 Lane Boyd over 4 years ago

TI__Genius 16845 points

Hi Gavin,

Y1 can meet the requirement if you have configured Y1 for PLL bypass mode. However, Y3 is synthesized from the PLL, it would not meet the requirement. I measured >>3psRMS for a similar configuration, but some optimization may be possible.

Kind regards,
Lane