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CDCM7005-SP: Duty cycle of reference clock signal

Part Number: CDCM7005-SP
Other Parts Discussed in Thread: CDCM7005

We have implemented a CDCM7005 in our equipment for clean clock generation. It synchronise to external 50 MHz reference clock and generate in particularly a clean 100 MHz. We have been informed by the customer the duty cycle of the external clock in a worst case condition could be 30 / 70%. My question is the following: is it still possible to operate the CDCM7005 with such clock knowing that this signal is divided by the PLL controller before to enter the phase comparator or do we have to add an external divided /2 stage to provide the PLL controller with in spec synchronisation clock. 

Thank you in advance for your answer.

Best regards