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CDCLVP1102: Relax product for input edge rate

Ryuuichi machida
Guru 11745 points
Part Number: CDCLVP1102

Hello,

I would like you to confirm any clock buffer which relax input transition time.

According to datasheet of CDCLVP1102, min input edge rate is min 1.5V/ns.

Then, I would like you to confirm solution of one of below.

1. Relax version of input transition time of CDCLVP1102 (Expected min 0.5 or 0.6V/ns)

2. 1ch LVCMOS clock buffer to improve SR (I confirmed TI logic product. There is spec for input transition time, however any one do NOT describe outout transition time in datasheet)

Condition from OSC is below.

* HCMOS output with 3.3V

* MAX output transition time is defined as 5ns (10%Vdd to 90%Vdd)

Best Regards,

  • 0
    TI__Guru* 88930 points

    Hi Machida-san,

    The additive jitter of a buffer depends on the skew rate of the input clock. A higher skew rate will result in lower additive jitter.

    The 1.5V/ns requirement means if the skew rate of the input clock is less than this, the measured additive jitter may be higher than datasheet specification. 

    The buffer will work even if the skew rate is less than 1.5V/ns. 

    FYI, usually the skew rate of a differential clock (e.g. LVDS, LVPECL) is higher than CMOS clock.