CDCE913: CDCE913 support in Linux version 4.14.0

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/i2c.h>
#include <linux/lcm.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>

#define CDCE913_NUM_OUTPUTS	3

/* CDCE913 registers */
#define CDCE913_GENERIC_CFG_0	0x80
#define CDCE913_GENERIC_CFG_1	0x81
#define CDCE913_GENERIC_CFG_2	0x82
#define CDCE913_GENERIC_CFG_3	0x83
#define CDCE913_GENERIC_CFG_4	0x84
#define CDCE913_GENERIC_CFG_5	0x85
#define CDCE913_GENERIC_CFG_6	0x86

#define CDCE913_PLL_CFG_0	0x90
#define CDCE913_PLL_CFG_1	0x91
#define CDCE913_PLL_CFG_2	0x92
#define CDCE913_PLL_CFG_3	0x93
#define CDCE913_PLL_CFG_4	0x94
#define CDCE913_PLL_CFG_5	0x95
#define CDCE913_PLL_CFG_6	0x96
#define CDCE913_PLL_CFG_7	0x97
#define CDCE913_PLL_CFG_8	0x98
#define CDCE913_PLL_CFG_9	0x99
#define CDCE913_PLL_CFG_10	0x9a
#define CDCE913_PLL_CFG_11	0x9b
#define CDCE913_PLL_CFG_12	0x9c
#define CDCE913_PLL_CFG_13	0x9d
#define CDCE913_PLL_CFG_14	0x9e
#define CDCE913_PLL_CFG_15	0x9f

/* bitfields */
#define GENERIC_CFG0_DEVID_SHIFT	7
#define GENERIC_CFG0_DEVID_MASK		(1 << GENERIC_CFG0_DEVID_SHIFT)
#define GENERIC_CFG0_REVID_SHIFT	4
#define GENERIC_CFG0_REVID_MASK		(7 << GENERIC_CFG0_REVID_SHIFT)
#define GENERIC_CFG0_VENDORID_SHIFT	0
#define GENERIC_CFG0_VENDORID_MASK	(0xf << GENERIC_CFG0_VENDORID_SHIFT)

#define PLLCFG_N_UPPER_SHIFT	4
#define PLLCFG_N_LOWER_SHIFT	4
#define PLLCFG_N_LOWER_MASK	(0xf << PLLCFG_N_LOWER_SHIFT)
#define PLLCFG_N_MAX		4095
#define PLLCFG_N_MIN		1

#define PLLCFG_M_MAX		511
#define PLLCFG_M_MIN		1

#define PLLCFG_R_UPPER_MASK	0xf
#define PLLCFG_R_LOWER_SHIFT	3
#define PLLCFG_R_LOWER_MASK	(0x1f << PLLCFG_R_LOWER_SHIFT)

#define PLLCFG_Q_UPPER_MASK	7
#define PLLCFG_Q_LOWER_SHIFT	5
#define PLLCFG_Q_LOWER_MASK	(7 << PLLCFG_Q_LOWER_SHIFT)

#define PLLCFG_P_SHIFT		2
#define PLLCFG_P_MASK		(7 << PLLCFG_P_SHIFT)

#define PDIV1_UPPER_MASK	3

#define XTAL_LOAD_CAP_SHIFT	3
#define XTAL_LOAD_CAP_MASK	(0x1f << XTAL_LOAD_CAP_SHIFT)

#define CLK_IN_TYPE_SHIFT	2
#define CLK_IN_TYPE_MASK	(3 << CLK_IN_TYPE_SHIFT)

#define F_VCO_MIN		80000000
#define F_VCO_MAX		230000000

/**
 * struct clk_cdce913:
 * @regmap:	Device's regmap
 * @i2c_client:	I2C client pointer
 * @clk_out:	Handles to output clocks
 * @clk_data:	Onecell data struct
 * @s0:		State of config pin S0
 * @fsbit:	State of FS bit
 */
struct clk_cdce913 {
	struct regmap		*regmap;
	struct i2c_client	*i2c_client;
	struct clk		*clk_out[CDCE913_NUM_OUTPUTS];
	struct clk_onecell_data	clk_data;
	int			s0;
	int			fsbit;
};

/**
 * struct clk_cdce913_pll:
 * @hw:		Clock handle
 * @frequency:	PLL frequency
 * @cdce913:	Pointer to driver struct
 */
struct clk_cdce913_pll {
	struct clk_hw		hw;
	unsigned long		frequency;
	struct clk_cdce913	*cdce913;
};
#define to_clk_cdce913_pll(_hw)	container_of(_hw, struct clk_cdce913_pll, hw)

/* CDCE913 PLL */
static int cdce913_read_pll_cfg(struct clk_cdce913 *cdce913, unsigned int *N,
		unsigned int *R, unsigned int *Q, unsigned int *P)
{
	int err, i;
	unsigned int addr;
	unsigned int regs[4];

	if (cdce913->fsbit)
		addr = CDCE913_PLL_CFG_12;
	else
		addr = CDCE913_PLL_CFG_8;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		err = regmap_read(cdce913->regmap, addr + i, &regs[i]);
		if (err)
			return err;
	}

	*N = (regs[0] << 4) |
		((regs[1] & PLLCFG_N_LOWER_MASK) >> PLLCFG_N_LOWER_SHIFT);
	*R = ((regs[1] & PLLCFG_R_UPPER_MASK) << 5) |
		((regs[2] & PLLCFG_R_LOWER_MASK) >> PLLCFG_R_LOWER_SHIFT);
	*Q = ((regs[2] & PLLCFG_Q_UPPER_MASK) << 3) |
		((regs[3] & PLLCFG_Q_LOWER_MASK) >> PLLCFG_Q_LOWER_SHIFT);
	*P = (regs[3] & PLLCFG_P_MASK) >> PLLCFG_P_SHIFT;

	/* TODO make dev_dbg */
	dev_info(&cdce913->i2c_client->dev, "%s: N=%u, R=%u, Q=%u, P=%u\n",
			__func__, *N, *R, *Q, *P);

	return 0;
}

static unsigned long cdce913_pll_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	int err;
	u64 rate;
	unsigned int N, R, Q, P;
	struct clk_cdce913_pll *pll = to_clk_cdce913_pll(hw);
	struct clk_cdce913 *cdce913 = pll->cdce913;

	err = cdce913_read_pll_cfg(cdce913, &N, &R, &Q, &P);
	if (err)
		return pll->frequency;

	rate = (N * Q) * (u64)parent_rate;
	rate = div_u64(rate, N * (1 << P) - R);

	pll->frequency = rate;

	return pll->frequency;
}

static int cdce913_pll_calc_divs(unsigned long rate, unsigned long parent_rate,
		unsigned int *N, int *R, unsigned int *Q, int *P)
{
	unsigned int NN, M, div;

	div = gcd(rate, parent_rate);

	*N = rate / div;
	M = parent_rate / div;

	if (*N > PLLCFG_N_MAX) {
		div = DIV_ROUND_UP(*N, PLLCFG_N_MAX);
		*N /= div;
		M /= div;
	}

	if (M > PLLCFG_M_MAX) {
		div = DIV_ROUND_UP(M, PLLCFG_M_MAX);
		*N /= div;
		M /= div;
	}

	if (!*N)
		*N = PLLCFG_N_MIN;
	if (!M)
		M = PLLCFG_M_MIN;

	if (*N < M)
		return -EINVAL;

	*P = 4 - ilog2(*N / M);
	if (*P < 0)
		*P = 0;

	if (*P > 7)
		return -EINVAL;

	NN = *N * (1 << *P);

	*Q = NN / M;
	if (*Q < 16 || *Q > 63)
		return -EINVAL;

	*R = NN - M * *Q;
	if (*R < 0 || *R > 511)
		return -EINVAL;

	return 0;
}

static long cdce913_pll_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	u64 rrate;
	int err, P, R;
	unsigned int N, Q;
	struct clk_cdce913_pll *pll = to_clk_cdce913_pll(hw);

	if (rate > F_VCO_MAX)
		rate = F_VCO_MAX;
	if (rate < F_VCO_MIN)
		rate = F_VCO_MIN;

	err = cdce913_pll_calc_divs(rate, *parent_rate, &N, &R, &Q, &P);
	if (err)
		return pll->frequency;

	rrate = (N * Q) * (u64)*parent_rate;
	rrate = div_u64(rrate, N * (1 << P) - R);

	return rrate;
}

static int cdce913_rate2range(unsigned long fvco)
{
	if (fvco < 125000000)
		return 0;

	if (fvco < 150000000)
		return 1;

	if (fvco < 175000000)
		return 2;

	return 3;
}

static int cdce913_write_pll_cfg(struct clk_cdce913 *cdce913, unsigned int N,
		unsigned int R, unsigned int Q, unsigned int P,
		unsigned int range)
{
	int err, i;
	unsigned int addr;
	unsigned int regs[4];

	if (cdce913->fsbit)
		addr = CDCE913_PLL_CFG_12;
	else
		addr = CDCE913_PLL_CFG_8;

	regs[0] = N >> PLLCFG_N_UPPER_SHIFT;

	regs[1] = (N << PLLCFG_N_LOWER_SHIFT) & PLLCFG_N_LOWER_MASK;
	regs[1] |= R >> 5;

	regs[2] = (R << PLLCFG_R_LOWER_SHIFT) & PLLCFG_R_LOWER_MASK;
	regs[2] |= Q >> 3;

	regs[3] = (Q << PLLCFG_Q_LOWER_SHIFT) & PLLCFG_Q_LOWER_MASK;
	regs[3] |= P << PLLCFG_P_SHIFT;
	regs[3] |= range;

	/* TODO remove dbg stuff */
	dev_info(&cdce913->i2c_client->dev, "%s: N=%u, R=%u, Q=%u, P=%u\n",
			__func__, N, R, Q, P);

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		err = regmap_write(cdce913->regmap, addr + i, regs[i]);
		if (err)
			return err;
	}

	/* TODO remove dbg stuff */
	cdce913_read_pll_cfg(cdce913, &N, &R, &Q, &P);

	return err;
}

static int cdce913_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	int err, P, R;
	unsigned int N, Q;
	struct clk_cdce913_pll *pll = to_clk_cdce913_pll(hw);
	struct clk_cdce913 *cdce913 = pll->cdce913;

	if (rate > F_VCO_MAX || rate < F_VCO_MIN)
		return -EINVAL;

	err = cdce913_pll_calc_divs(rate, parent_rate, &N, &R, &Q, &P);
	if (err)
		return err;

	/* write to HW */
	return cdce913_write_pll_cfg(cdce913, N, R, Q, P,
			cdce913_rate2range(rate));
}

static struct clk_ops cdce913_pll_ops = {
	.recalc_rate = cdce913_pll_recalc_rate,
	.round_rate = cdce913_pll_round_rate,
	.set_rate = cdce913_pll_set_rate,
};

static struct clk *clk_register_cdce913_pll(struct clk_cdce913 *cdce913,
		const char *name, const char *parent)
{
	struct clk *clk;
	const char *pll_name;
	struct clk_init_data init;
	struct clk_cdce913_pll *data;
	const char *parents[] = {parent};

	data = devm_kzalloc(&cdce913->i2c_client->dev, sizeof(*data),
			GFP_KERNEL);
	if (!data)
		return ERR_PTR(-ENOMEM);

	pll_name = kasprintf(GFP_KERNEL, "%s_pll", name);
	if (!pll_name)
		return ERR_PTR(-ENOMEM);

	init.ops = &cdce913_pll_ops;
	init.name = pll_name;
	init.num_parents = 1;
	init.parent_names = parents;
	data->hw.init = &init;
	data->cdce913 = cdce913;

	clk = devm_clk_register(&cdce913->i2c_client->dev, &data->hw);

	kfree(pll_name);

	return clk;
}

/* PDIV1 accessors */
static unsigned int pdiv1_get_div(struct clk_i2c_divider *divider)
{
	int err, i;
	unsigned int regs[2];
	unsigned int div;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		err = regmap_read(divider->regmap, divider->reg + i, &regs[i]);
		if (err)
			break;
	}
	if (err) {
		pr_err("%s: reading from device failed\n", __func__);
		return 1;
	}

	div = (regs[0] & PDIV1_UPPER_MASK) << 8;
	div |= regs[1];

	return div;
}

static int pdiv1_set_div(unsigned int div, struct clk_i2c_divider *divider)
{
	int err, i;
	unsigned int regs[2];

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		err = regmap_read(divider->regmap, divider->reg + i, &regs[i]);
		if (err)
			return err;
	}

	regs[1] = div & 0xff;

	regs[0] &= ~PDIV1_UPPER_MASK;
	div >>= 8;
	div &= PDIV1_UPPER_MASK;
	regs[0] |= div;

	for (i = 0; i < ARRAY_SIZE(regs); i++) {
		err = regmap_write(divider->regmap, divider->reg + i, regs[i]);
		if (err)
			return err;
	}

	return 0;
}

/* regmap functions */
static bool cdce913_regmap_is_volatile(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CDCE913_GENERIC_CFG_1:
		return true;
	default:
		return false;
	}
}

static bool cdce913_regmap_is_writeable(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CDCE913_GENERIC_CFG_1 ... CDCE913_GENERIC_CFG_6:
		return true;
	case CDCE913_PLL_CFG_0 ... CDCE913_PLL_CFG_15:
		return true;
	default:
		return false;
	}
}

static struct regmap_config cdce913_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.cache_type = REGCACHE_RBTREE,
	.max_register = CDCE913_PLL_CFG_15,
	.writeable_reg = cdce913_regmap_is_writeable,
	.volatile_reg = cdce913_regmap_is_volatile,
};

/**
 * cdce913_get_part_id() - Read part identification
 * @cdce913:	Driver data structure
 * @dev:	Part ID (output)
 * @rev:	Part revision (output)
 * @ven:	Vendor ID (output)
 * Returns 0 on success, or passes on regmap_read() error.
 */
static int cdce913_get_part_id(struct clk_cdce913 *cdce913, unsigned int *dev,
		unsigned int *rev, unsigned int *ven)
{
	int err;
	unsigned int reg;

	err = regmap_read(cdce913->regmap, CDCE913_GENERIC_CFG_0, &reg);
	if (err)
		return err;

	*rev = (reg & GENERIC_CFG0_REVID_MASK) >> GENERIC_CFG0_DEVID_SHIFT;
	*ven = (reg & GENERIC_CFG0_VENDORID_MASK) >> GENERIC_CFG0_VENDORID_SHIFT;
	*dev = (reg & GENERIC_CFG0_DEVID_MASK) >> GENERIC_CFG0_DEVID_SHIFT;

	return 0;
}

/**
 * cdce913_set_clk_in_type() - Set input clock type
 * @cdce913:		Driver data structure
 * @clk_in_type:	String describing input clock type
 *
 * Set the input clock type according to the provided DT property. Valid types
 * are 'xtal', 'VCXO', 'LVCMOS'.
 */
static void cdce913_set_clk_in_type(struct clk_cdce913 *cdce913,
		const char *clk_in_type)
{
	int err;
	unsigned int type, reg;
	/*
	 * Valid types are xtal, VCXO, LVCMOS, let's do a lazy compare of the
	 * first letter only and save us all the strcmp overhead
	 */
	switch (clk_in_type[0]) {
	case 'V':
		type = 1;
		break;
	case 'L':
		type = 2;
		break;
	default:
		type = 0;
		break;
	}

	err = regmap_read(cdce913->regmap, CDCE913_GENERIC_CFG_1, &reg);
	if (err) {
		dev_err(&cdce913->i2c_client->dev, "read from device failed\n");
		return;
	}

	reg &= ~CLK_IN_TYPE_MASK;
	reg |= type << CLK_IN_TYPE_SHIFT;

	err = regmap_write(cdce913->regmap, CDCE913_GENERIC_CFG_1, reg);
	if (err) {
		dev_err(&cdce913->i2c_client->dev, "write to device failed\n");
		return;
	}
}

static void cdce913_init_frequencies(struct device_node *np,
		struct clk_cdce913 *data, struct clk *pll)
{
	int err, i;
	u32 fout[3];
	unsigned long fvco;
	struct device *dev = &data->i2c_client->dev;

	err = of_property_read_u32_array(np, "clock-frequency", fout,
			ARRAY_SIZE(fout));
	if (err)
		return;

	for (i = 0; i < ARRAY_SIZE(fout); i++) {
		if (fout[i] > F_VCO_MAX) {
			dev_warn(dev, "requested output frequency '%u' exceeds maximum (%u)\n",
					fout[i], F_VCO_MAX);
			fout[i] = F_VCO_MAX;
		}
	}

	fvco = lcm(fout[0] / 1000000, fout[1] / 1000000);
	fvco = lcm(fvco, fout[2] / 1000000);
	fvco *= 1000000;

	if (fvco > F_VCO_MAX) {
		dev_warn(dev, "requested VCO frequency '%lu' exceeds maximum (%u)\n",
				fvco, F_VCO_MAX);
		fvco = F_VCO_MAX;
	}

	if (fvco < F_VCO_MIN) {
		dev_warn(dev, "requested VCO frequency '%lu' below minimum (%u)\n",
				fvco, F_VCO_MIN);
		fvco = F_VCO_MIN;
	}

	err = clk_set_rate(pll, fvco);
	if (err)
		return;

	/* TODO dev_dbg */
	dev_info(dev, "VCO frequency: %lu Hz\n", clk_get_rate(pll));

	for (i = 0; i < ARRAY_SIZE(fout); i++) {
		if (fout[i])
			clk_set_rate(data->clk_out[i], fout[i]);
	}
}

static int cdce913_probe(struct i2c_client *client,
		const struct i2c_device_id *id)
{
	int err;
	unsigned int part, revision, vendor, cap;
	struct clk_cdce913 *data;
	struct clk *pll, *pll_mux, *y1_mux, *y2_mux, *y3_mux;
	struct clk *pdiv1, *pdiv2, *pdiv3;
	const char *pname, *pll_mux_name, *clk_in_type;
	const char *y1_mux_name, *y2_mux_name, *y3_mux_name;
	const char *pdiv1_name, *pdiv2_name, *pdiv3_name;
	const char *pll_mux_parents[2];
	const char *y1_mux_parents[2], *y2_mux_parents[2], *y3_mux_parents[3];
	struct device_node *np = client->dev.of_node;

	data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->i2c_client = client;

	data->regmap = devm_regmap_init_i2c(client, &cdce913_regmap_config);
	if (IS_ERR(data->regmap)) {
		dev_err(&client->dev, "failed to allocate register map\n");
		return PTR_ERR(data->regmap);
	}

	err = of_property_read_u32(np, "ti,s0", &data->s0);
	if (err) {
		dev_warn(&client->dev, "S0 not specified, assuming 1\n");
		data->s0 = 1;
	}

	err = regmap_read(data->regmap, CDCE913_PLL_CFG_3, &data->fsbit);
	if (err) {
		dev_warn(&client->dev, "unable to read from device\n");
		return err;
	}
	data->fsbit = !!(data->fsbit & (1 << data->s0));

	i2c_set_clientdata(client, data);

	err = cdce913_get_part_id(data, &part, &revision, &vendor);
	if (err)
		return err;

	pname = of_clk_get_parent_name(np, 0);
	if (!pname) {
		dev_err(&client->dev, "no input clock specified\n");
		return -ENODEV;
	}

	/* PLL */
	pll = clk_register_cdce913_pll(data, np->name, pname);
	if (IS_ERR(pll)) {
		dev_err(&client->dev, "clock registration failed\n");
		return PTR_ERR(pll);
	}

	/* PLL mux */
	pll_mux_name = kasprintf(GFP_KERNEL, "%s_pll_mux", np->name);
	if (!pll_mux_name)
		return -ENOMEM;

	pll_mux_parents[0] = __clk_get_name(pll);
	pll_mux_parents[1] = pname;
	pll_mux = clk_i2c_register_mux(&client->dev, pll_mux_name,
			pll_mux_parents, 2, CLK_SET_RATE_PARENT, data->regmap,
			CDCE913_PLL_CFG_4, 7, 1, 0);
	if (IS_ERR(pll_mux)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(pll_mux);
		goto err_pll_mux;
	}

	/* use PLL */
	err = clk_set_parent(pll_mux, pll);
	if (err)
		dev_warn(&client->dev, "PLL in bypass\n");

	/* Y1 mux */
	y1_mux_name = kasprintf(GFP_KERNEL, "%s_y1_mux", np->name);
	if (!y1_mux_name) {
		err = -ENOMEM;
		goto err_pll_mux;
	}

	y1_mux_parents[0] = pname;
	y1_mux_parents[1] = pll_mux_name;
	y1_mux = clk_i2c_register_mux(&client->dev, y1_mux_name,
			y1_mux_parents, 2,
			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
			data->regmap, CDCE913_GENERIC_CFG_2, 7, 1, 0);
	if (IS_ERR(y1_mux)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(y1_mux);
		goto err_y1_mux;
	}

	/* pdiv1 */
	pdiv1_name = kasprintf(GFP_KERNEL, "%s_pdiv1", np->name);
	if (!pdiv1_name) {
		err = -ENOMEM;
		goto err_y1_mux;
	}

	pdiv1 = clk_i2c_register_divider(&client->dev, pdiv1_name, y1_mux_name,
			CLK_SET_RATE_PARENT, data->regmap, CDCE913_GENERIC_CFG_2, 0, 10,
			CLK_DIVIDER_ONE_BASED, pdiv1_get_div, pdiv1_set_div);
	if (IS_ERR(pdiv1)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(pdiv1);
		goto err_pdiv1;
	}

	/* pdiv2 */
	pdiv2_name = kasprintf(GFP_KERNEL, "%s_pdiv2", np->name);
	if (!pdiv2_name) {
		err = -ENOMEM;
		goto err_pdiv1;
	}

	pdiv2 = clk_i2c_register_divider(&client->dev, pdiv2_name,
			pll_mux_name, CLK_SET_RATE_PARENT, data->regmap,
			CDCE913_PLL_CFG_6, 0, 7, CLK_DIVIDER_ONE_BASED, NULL,
			NULL);
	if (IS_ERR(pdiv2)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(pdiv2);
		goto err_pdiv2;
	}

	/* pdiv3 */
	pdiv3_name = kasprintf(GFP_KERNEL, "%s_pdiv3", np->name);
	if (!pdiv3_name) {
		err = -ENOMEM;
		goto err_pdiv2;
	}

	pdiv3 = clk_i2c_register_divider(&client->dev, pdiv3_name,
			pll_mux_name, CLK_SET_RATE_PARENT, data->regmap,
			CDCE913_PLL_CFG_7, 0, 7, CLK_DIVIDER_ONE_BASED, NULL,
			NULL);
	if (IS_ERR(pdiv3)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(pdiv3);
		goto err_pdiv3;
	}

	/* Y2 mux */
	y2_mux_name = kasprintf(GFP_KERNEL, "%s_y2_mux", np->name);
	if (!y2_mux_name) {
		err = -ENOMEM;
		goto err_pdiv3;
	}

	y2_mux_parents[0] = pdiv1_name;
	y2_mux_parents[1] = pdiv2_name;
	y2_mux = clk_i2c_register_mux(&client->dev, y2_mux_name,
			y2_mux_parents, 2,
			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
			data->regmap, CDCE913_PLL_CFG_4, 6, 1, 0);
	if (IS_ERR(y2_mux)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(y2_mux);
		goto err_y2_mux;
	}

	/* Y3 mux */
	y3_mux_name = kasprintf(GFP_KERNEL, "%s_y3_mux", np->name);
	if (!y3_mux_name) {
		err = -ENOMEM;
		goto err_y2_mux;
	}

	y3_mux_parents[0] = pdiv1_name;
	y3_mux_parents[1] = pdiv2_name;
	y3_mux_parents[2] = pdiv3_name;
	y3_mux = clk_i2c_register_mux(&client->dev, y3_mux_name,
			y3_mux_parents, 3,
			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
			data->regmap, CDCE913_PLL_CFG_4, 4, 2, 0);
	if (IS_ERR(y3_mux)) {
		dev_err(&client->dev, "clock registration failed\n");
		err = PTR_ERR(y3_mux);
		goto err_y3_mux;
	}

	err = of_property_read_u32(np, "ti,crystal-load-capacity", &cap);
	if (!err) {
		if (cap > 20)
			cap = 20;
		cap <<= XTAL_LOAD_CAP_SHIFT;
		err = regmap_write(data->regmap, CDCE913_GENERIC_CFG_5, cap);
		if (err)
			dev_warn(&client->dev, "unable to write to device\n");
	}

	err = of_property_read_string(np, "ti,input-clock-type", &clk_in_type);
	if (!err)
		cdce913_set_clk_in_type(data, clk_in_type);

err_y3_mux:
	kfree(y3_mux_name);
err_y2_mux:
	kfree(y2_mux_name);
err_pdiv3:
	kfree(pdiv3_name);
err_pdiv2:
	kfree(pdiv2_name);
err_pdiv1:
	kfree(pdiv1_name);
err_y1_mux:
	kfree(y1_mux_name);
err_pll_mux:
	kfree(pll_mux_name);

	if (err)
		return err;

	data->clk_out[0] = pdiv1;
	data->clk_out[1] = y2_mux;
	data->clk_out[2] = y3_mux;

	data->clk_data.clks = data->clk_out;
	data->clk_data.clk_num = ARRAY_SIZE(data->clk_out);
	err = of_clk_add_provider(np, of_clk_src_onecell_get, &data->clk_data);
	if (err)
		goto err_clk_provider;

	cdce913_init_frequencies(np, data, pll);

	dev_info(&client->dev, "%s %u/%u: current frequencies: %lu, %lu, %lu\n",
			part ? "CDCE913" : "CDCEL913", vendor, revision,
			clk_get_rate(data->clk_out[0]),
			clk_get_rate(data->clk_out[1]),
			clk_get_rate(data->clk_out[2]));

err_clk_provider:
	return err;
}

static int cdce913_remove(struct i2c_client *client)
{
	of_clk_del_provider(client->dev.of_node);
	return 0;
}

static const struct i2c_device_id cdce913_id[] = {
	{ "cdce913" },
	{ "cdcel913" },
	{ }
};
MODULE_DEVICE_TABLE(i2c, cdce_id);

static const struct of_device_id clk_cdce913_of_match[] = {
	{ .compatible = "ti,cdce913" },
	{ .compatible = "ti,cdcel913" },
	{ },
};
MODULE_DEVICE_TABLE(of, clk_cdce913_of_match);

static struct i2c_driver cdce913_driver = {
	.driver = {
		.name = "cdce913",
		.of_match_table = of_match_ptr(clk_cdce913_of_match),
	},
	.probe		= cdce913_probe,
	.remove		= cdce913_remove,
	.id_table	= cdce913_id,
};
module_i2c_driver(cdce913_driver);

MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
MODULE_DESCRIPTION("CDCE913 driver");
MODULE_LICENSE("GPL");

/*
 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
 *
 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
 * basis. Clients can directly request any frequency that the chip can
 * deliver using the standard clk framework. In addition, the device can
 * be configured and activated via the devicetree.
 *
 * Copyright (C) 2014, Topic Embedded Products
 * Licenced under GPL
 */
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/gcd.h>

/* Each chip has different number of PLLs and outputs, for example:
 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
 * Model this as 2 PLL clocks which are parents to the outputs.
 */

enum {
	CDCE913,
	CDCE925,
	CDCE937,
	CDCE949,
};

struct clk_cdce925_chip_info {
	int num_plls;
	int num_outputs;
};

static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
	[CDCE913] = { .num_plls = 1, .num_outputs = 3 },
	[CDCE925] = { .num_plls = 2, .num_outputs = 5 },
	[CDCE937] = { .num_plls = 3, .num_outputs = 7 },
	[CDCE949] = { .num_plls = 4, .num_outputs = 9 },
};

#define MAX_NUMBER_OF_PLLS	4
#define MAX_NUMBER_OF_OUTPUTS	9

#define CDCE925_REG_GLOBAL1	0x81
#define CDCE925_REG_Y1SPIPDIVH	0x82
#define CDCE925_REG_PDIVL	0x83
#define CDCE925_REG_XCSEL	0x85
/* PLL parameters start at 0x10, steps of 0x10 */
#define CDCE925_OFFSET_PLL	0x90
/* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
#define CDCE925_PLL_MUX_OUTPUTS	0x94
#define CDCE925_PLL_MULDIV	0x98

#define CDCE925_PLL_FREQUENCY_MIN	 80000000ul
#define CDCE925_PLL_FREQUENCY_MAX	230000000ul
struct clk_cdce925_chip;

struct clk_cdce925_output {
	struct clk_hw hw;
	struct clk_cdce925_chip *chip;
	u8 index;
	u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
};
#define to_clk_cdce925_output(_hw) \
	container_of(_hw, struct clk_cdce925_output, hw)

struct clk_cdce925_pll {
	struct clk_hw hw;
	struct clk_cdce925_chip *chip;
	u8 index;
	u16 m;   /* 1..511 */
	u16 n;   /* 1..4095 */
};
#define to_clk_cdce925_pll(_hw)	container_of(_hw, struct clk_cdce925_pll, hw)

struct clk_cdce925_chip {
	struct regmap *regmap;
	struct i2c_client *i2c_client;
	const struct clk_cdce925_chip_info *chip_info;
	struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
	struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
};

/* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */

static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
	u16 n, u16 m)
{
	if ((!m || !n) || (m == n))
		return parent_rate; /* In bypass mode runs at same frequency */
	return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
}

static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	/* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);

	return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
}

static void cdce925_pll_find_rate(unsigned long rate,
		unsigned long parent_rate, u16 *n, u16 *m)
{
	unsigned long un;
	unsigned long um;
	unsigned long g;

	if (rate <= parent_rate) {
		/* Can always deliver parent_rate in bypass mode */
		rate = parent_rate;
		*n = 0;
		*m = 0;
	} else {
		/* In PLL mode, need to apply min/max range */
		if (rate < CDCE925_PLL_FREQUENCY_MIN)
			rate = CDCE925_PLL_FREQUENCY_MIN;
		else if (rate > CDCE925_PLL_FREQUENCY_MAX)
			rate = CDCE925_PLL_FREQUENCY_MAX;

		g = gcd(rate, parent_rate);
		um = parent_rate / g;
		un = rate / g;
		/* When outside hw range, reduce to fit (rounding errors) */
		while ((un > 4095) || (um > 511)) {
			un >>= 1;
			um >>= 1;
		}
		if (un == 0)
			un = 1;
		if (um == 0)
			um = 1;

		*n = un;
		*m = um;
	}
}

static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	u16 n, m;

	cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
	return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
}

static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);

	if (!rate || (rate == parent_rate)) {
		data->m = 0; /* Bypass mode */
		data->n = 0;
		return 0;
	}

	if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
		(rate > CDCE925_PLL_FREQUENCY_MAX)) {
		pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
		return -EINVAL;
	}

	if (rate < parent_rate) {
		pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
			rate, parent_rate);
		return -EINVAL;
	}

	cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
	return 0;
}


/* calculate p = max(0, 4 - int(log2 (n/m))) */
static u8 cdce925_pll_calc_p(u16 n, u16 m)
{
	u8 p;
	u16 r = n / m;

	if (r >= 16)
		return 0;
	p = 4;
	while (r > 1) {
		r >>= 1;
		--p;
	}
	return p;
}
/* Returns VCO range bits for VCO1_0_RANGE */
static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
{
	struct clk *parent = clk_get_parent(hw->clk);
	unsigned long rate = clk_get_rate(parent);

	rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
	if (rate >= 175000000)
		return 0x3;
	if (rate >= 150000000)
		return 0x02;
	if (rate >= 125000000)
		return 0x01;
	return 0x00;
}

/* I2C clock, hence everything must happen in (un)prepare because this
 * may sleep */
static int cdce925_pll_prepare(struct clk_hw *hw)
{
	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
	u16 n = data->n;
	u16 m = data->m;
	u16 r;
	u8 q;
	u8 p;
	u16 nn;
	u8 pll[4]; /* Bits are spread out over 4 byte registers */
	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
	unsigned i;

	if ((!m || !n) || (m == n)) {
		/* Set PLL mux to bypass mode, leave the rest as is */
		regmap_update_bits(data->chip->regmap,
			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
	} else {
		/* According to data sheet: */
		/* p = max(0, 4 - int(log2 (n/m))) */
		p = cdce925_pll_calc_p(n, m);
		/* nn = n * 2^p */
		nn = n * BIT(p);
		/* q = int(nn/m) */
		q = nn / m;
		if ((q < 16) || (q > 63)) {
			pr_debug("%s invalid q=%d\n", __func__, q);
			return -EINVAL;
		}
		r = nn - (m*q);
		if (r > 511) {
			pr_debug("%s invalid r=%d\n", __func__, r);
			return -EINVAL;
		}
		pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
			n, m, p, q, r);
		/* encode into register bits */
		pll[0] = n >> 4;
		pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
		pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
		pll[3] = ((q & 0x07) << 5) | (p << 2) |
				cdce925_pll_calc_range_bits(hw, n, m);
		/* Write to registers */
		for (i = 0; i < ARRAY_SIZE(pll); ++i)
			regmap_write(data->chip->regmap,
				reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
		/* Enable PLL */
		regmap_update_bits(data->chip->regmap,
			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
	}

	return 0;
}

static void cdce925_pll_unprepare(struct clk_hw *hw)
{
	struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
	u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;

	regmap_update_bits(data->chip->regmap,
			reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
}

static const struct clk_ops cdce925_pll_ops = {
	.prepare = cdce925_pll_prepare,
	.unprepare = cdce925_pll_unprepare,
	.recalc_rate = cdce925_pll_recalc_rate,
	.round_rate = cdce925_pll_round_rate,
	.set_rate = cdce925_pll_set_rate,
};


static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
{
	switch (data->index) {
	case 0:
		regmap_update_bits(data->chip->regmap,
			CDCE925_REG_Y1SPIPDIVH,
			0x03, (pdiv >> 8) & 0x03);
		regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
		break;
	case 1:
		regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
		break;
	case 2:
		regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
		break;
	case 3:
		regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
		break;
	case 4:
		regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
		break;
	case 5:
		regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
		break;
	case 6:
		regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
		break;
	case 7:
		regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
		break;
	case 8:
		regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
		break;
	}
}

static void cdce925_clk_activate(struct clk_cdce925_output *data)
{
	switch (data->index) {
	case 0:
		regmap_update_bits(data->chip->regmap,
			CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
		break;
	case 1:
	case 2:
		regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
		break;
	case 3:
	case 4:
		regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
		break;
	case 5:
	case 6:
		regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
		break;
	case 7:
	case 8:
		regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
		break;
	}
}

static int cdce925_clk_prepare(struct clk_hw *hw)
{
	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);

	cdce925_clk_set_pdiv(data, data->pdiv);
	cdce925_clk_activate(data);
	return 0;
}

static void cdce925_clk_unprepare(struct clk_hw *hw)
{
	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);

	/* Disable clock by setting divider to "0" */
	cdce925_clk_set_pdiv(data, 0);
}

static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);

	if (data->pdiv)
		return parent_rate / data->pdiv;
	return 0;
}

static u16 cdce925_calc_divider(unsigned long rate,
		unsigned long parent_rate)
{
	unsigned long divider;

	if (!rate)
		return 0;
	if (rate >= parent_rate)
		return 1;

	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
	if (divider > 0x7F)
		divider = 0x7F;

	return (u16)divider;
}

static unsigned long cdce925_clk_best_parent_rate(
	struct clk_hw *hw, unsigned long rate)
{
	struct clk *pll = clk_get_parent(hw->clk);
	struct clk *root = clk_get_parent(pll);
	unsigned long root_rate = clk_get_rate(root);
	unsigned long best_rate_error = rate;
	u16 pdiv_min;
	u16 pdiv_max;
	u16 pdiv_best;
	u16 pdiv_now;

	if (root_rate % rate == 0)
		return root_rate; /* Don't need the PLL, use bypass */

	pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
	pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);

	if (pdiv_min > pdiv_max)
		return 0; /* No can do? */

	pdiv_best = pdiv_min;
	for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
		unsigned long target_rate = rate * pdiv_now;
		long pll_rate = clk_round_rate(pll, target_rate);
		unsigned long actual_rate;
		unsigned long rate_error;

		if (pll_rate <= 0)
			continue;
		actual_rate = pll_rate / pdiv_now;
		rate_error = abs((long)actual_rate - (long)rate);
		if (rate_error < best_rate_error) {
			pdiv_best = pdiv_now;
			best_rate_error = rate_error;
		}
		/* TODO: Consider PLL frequency based on smaller n/m values
		 * and pick the better one if the error is equal */
	}

	return rate * pdiv_best;
}

static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	unsigned long l_parent_rate = *parent_rate;
	u16 divider = cdce925_calc_divider(rate, l_parent_rate);

	if (l_parent_rate / divider != rate) {
		l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
		divider = cdce925_calc_divider(rate, l_parent_rate);
		*parent_rate = l_parent_rate;
	}

	if (divider)
		return (long)(l_parent_rate / divider);
	return 0;
}

static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);

	data->pdiv = cdce925_calc_divider(rate, parent_rate);

	return 0;
}

static const struct clk_ops cdce925_clk_ops = {
	.prepare = cdce925_clk_prepare,
	.unprepare = cdce925_clk_unprepare,
	.recalc_rate = cdce925_clk_recalc_rate,
	.round_rate = cdce925_clk_round_rate,
	.set_rate = cdce925_clk_set_rate,
};


static u16 cdce925_y1_calc_divider(unsigned long rate,
		unsigned long parent_rate)
{
	unsigned long divider;

	if (!rate)
		return 0;
	if (rate >= parent_rate)
		return 1;

	divider = DIV_ROUND_CLOSEST(parent_rate, rate);
	if (divider > 0x3FF) /* Y1 has 10-bit divider */
		divider = 0x3FF;

	return (u16)divider;
}

static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
{
	unsigned long l_parent_rate = *parent_rate;
	u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);

	if (divider)
		return (long)(l_parent_rate / divider);
	return 0;
}

static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{
	struct clk_cdce925_output *data = to_clk_cdce925_output(hw);

	data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);

	return 0;
}

static const struct clk_ops cdce925_clk_y1_ops = {
	.prepare = cdce925_clk_prepare,
	.unprepare = cdce925_clk_unprepare,
	.recalc_rate = cdce925_clk_recalc_rate,
	.round_rate = cdce925_clk_y1_round_rate,
	.set_rate = cdce925_clk_y1_set_rate,
};

#define CDCE925_I2C_COMMAND_BLOCK_TRANSFER	0x00
#define CDCE925_I2C_COMMAND_BYTE_TRANSFER	0x80

static int cdce925_regmap_i2c_write(
	void *context, const void *data, size_t count)
{
	struct device *dev = context;
	struct i2c_client *i2c = to_i2c_client(dev);
	int ret;
	u8 reg_data[2];

	if (count != 2)
		return -ENOTSUPP;

	/* First byte is command code */
	reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
	reg_data[1] = ((u8 *)data)[1];

	dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
			reg_data[0], reg_data[1]);

	ret = i2c_master_send(i2c, reg_data, count);
	if (likely(ret == count))
		return 0;
	else if (ret < 0)
		return ret;
	else
		return -EIO;
}

static int cdce925_regmap_i2c_read(void *context,
	   const void *reg, size_t reg_size, void *val, size_t val_size)
{
	struct device *dev = context;
	struct i2c_client *i2c = to_i2c_client(dev);
	struct i2c_msg xfer[2];
	int ret;
	u8 reg_data[2];

	if (reg_size != 1)
		return -ENOTSUPP;

	xfer[0].addr = i2c->addr;
	xfer[0].flags = 0;
	xfer[0].buf = reg_data;
	if (val_size == 1) {
		reg_data[0] =
			CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
		xfer[0].len = 1;
	} else {
		reg_data[0] =
			CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
		reg_data[1] = val_size;
		xfer[0].len = 2;
	}

	xfer[1].addr = i2c->addr;
	xfer[1].flags = I2C_M_RD;
	xfer[1].len = val_size;
	xfer[1].buf = val;

	ret = i2c_transfer(i2c->adapter, xfer, 2);
	if (likely(ret == 2)) {
		dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
				reg_size, val_size, reg_data[0], *((u8 *)val));
		return 0;
	} else if (ret < 0)
		return ret;
	else
		return -EIO;
}

static struct clk_hw *
of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
{
	struct clk_cdce925_chip *data = _data;
	unsigned int idx = clkspec->args[0];

	if (idx >= ARRAY_SIZE(data->clk)) {
		pr_err("%s: invalid index %u\n", __func__, idx);
		return ERR_PTR(-EINVAL);
	}

	return &data->clk[idx].hw;
}

/* The CDCE925 uses a funky way to read/write registers. Bulk mode is
 * just weird, so just use the single byte mode exclusively. */
static struct regmap_bus regmap_cdce925_bus = {
	.write = cdce925_regmap_i2c_write,
	.read = cdce925_regmap_i2c_read,
};

static int cdce925_probe(struct i2c_client *client,
		const struct i2c_device_id *id)
{
	struct clk_cdce925_chip *data;
	struct device_node *node = client->dev.of_node;
	const char *parent_name;
	const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
	struct clk_init_data init;
	u32 value;
	int i;
	int err;
	struct device_node *np_output;
	char child_name[6];
	struct regmap_config config = {
		.name = "configuration0",
		.reg_bits = 8,
		.val_bits = 8,
		.cache_type = REGCACHE_RBTREE,
	};
        printk("clock test ...................!!!!!!!!!!!!!!!!!!!!!\n");
	dev_dbg(&client->dev, "%s\n", __func__);
	data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->i2c_client = client;
	data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
        printk("number of PLL------------------------- %d",data->chip_info->num_plls);
	config.max_register = CDCE925_OFFSET_PLL +
		data->chip_info->num_plls * 0x10 - 1;
	data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus,
			&client->dev, &config);
	if (IS_ERR(data->regmap)) {
		dev_err(&client->dev, "failed to allocate register map\n");
		return PTR_ERR(data->regmap);
	}
	i2c_set_clientdata(client, data);

	parent_name = of_clk_get_parent_name(node, 0);
        printk("Parent name = %s\n", parent_name);
	if (!parent_name) {
		dev_err(&client->dev, "missing parent clock\n");
		return -ENODEV;
	}
	dev_dbg(&client->dev, "parent is: %s\n", parent_name);

	if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
		regmap_write(data->regmap,
			CDCE925_REG_XCSEL, (value << 3) & 0xF8);
	/* PWDN bit */
	regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);

	/* Set input source for Y1 to be the XTAL */
	regmap_update_bits(data->regmap, 0x02, BIT(7), 0);

	init.ops = &cdce925_pll_ops;
	init.flags = 0;
	init.parent_names = &parent_name;
	init.num_parents = parent_name ? 1 : 0;

	/* Register PLL clocks */
	for (i = 0; i < data->chip_info->num_plls; ++i) {
		pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
			client->dev.of_node->name, i);
		init.name = pll_clk_name[i];
		data->pll[i].chip = data;
		data->pll[i].hw.init = &init;
		data->pll[i].index = i;
		err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
                printk(" devm_clk_hw_register %d\n",err);
		if (err) {
			dev_err(&client->dev, "Failed register PLL %d\n", i);
			goto error;
		}
		sprintf(child_name, "PLL%d", i+1);
                
                printk( "child name %s\n", child_name);
		np_output = of_get_child_by_name(node, child_name);
		if (!np_output)
			continue;
                value = 0;
                printk( "after continue\n");
		if (!of_property_read_u32(np_output,
			"clock-frequency", &value)) {
			err = clk_set_rate(data->pll[i].hw.clk, value);
                        printk("err =============%d\n" , err);
			if (err)
				dev_err(&client->dev,
					"unable to set PLL frequency %ud\n",
					value);
printk("set frequency value = %ud\n", value);

		}

printk("1111 set frequency value = %d\n", value);
		if (!of_property_read_u32(np_output,
			"spread-spectrum", &value)) {
			u8 flag = of_property_read_bool(np_output,
				"spread-spectrum-center") ? 0x80 : 0x00;
			regmap_update_bits(data->regmap,
				0x16 + (i*CDCE925_OFFSET_PLL),
				0x80, flag);
			regmap_update_bits(data->regmap,
				0x12 + (i*CDCE925_OFFSET_PLL),
				0x07, value & 0x07);
		}
	}

	/* Register output clock Y1 */
	init.ops = &cdce925_clk_y1_ops;
	init.flags = 0;
	init.num_parents = 1;
	init.parent_names = &parent_name; /* Mux Y1 to input */
	init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name);
	data->clk[0].chip = data;
	data->clk[0].hw.init = &init;
	data->clk[0].index = 0;
	data->clk[0].pdiv = 1;
	err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
        printk("devm_clk_hw_register %d\n" , err);
	kfree(init.name); /* clock framework made a copy of the name */
	if (err) {
		dev_err(&client->dev, "clock registration Y1 failed\n");
		goto error;
	}
printk("number of outputs----------%d\n", data->chip_info->num_outputs);
	/* Register output clocks Y2 .. Y5*/
	init.ops = &cdce925_clk_ops;
	init.flags = CLK_SET_RATE_PARENT;
	init.num_parents = 1;
	for (i = 1; i < data->chip_info->num_outputs; ++i) {
		init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
			client->dev.of_node->name, i+1);
		data->clk[i].chip = data;
		data->clk[i].hw.init = &init;
		data->clk[i].index = i;
		data->clk[i].pdiv = 1;
		switch (i) {
		case 1:
		case 2:
			/* Mux Y2/3 to PLL1 */
                       
			init.parent_names = &pll_clk_name[0];
                        printk("parent name = %s\n", pll_clk_name[0]);
			break;
		case 3:
		case 4:

			/* Mux Y4/5 to PLL2 */
			init.parent_names = &pll_clk_name[1];
			break;
		case 5:
		case 6:

			/* Mux Y6/7 to PLL3 */
			init.parent_names = &pll_clk_name[2];
			break;
		case 7:
		case 8:

			/* Mux Y8/9 to PLL4 */
			init.parent_names = &pll_clk_name[3];
			break;
		}
		err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
                printk("devm_clk_hw_register %d\n" , err);
		kfree(init.name); /* clock framework made a copy of the name */
		if (err) {
			dev_err(&client->dev, "clock registration failed\n");
			goto error;
		}
	}

	/* Register the output clocks */
	err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
				  data);
        printk("of_clk_add_hw_provider %d\n" , err);
	if (err)
		dev_err(&client->dev, "unable to add OF clock provider\n");

	err = 0;

error:
	for (i = 0; i < data->chip_info->num_plls; ++i)
		/* clock framework made a copy of the name */
		kfree(pll_clk_name[i]);

	return err;
}

static const struct i2c_device_id cdce925_id[] = {
	{ "cdce913", CDCE913 },
	{ "cdce925", CDCE925 },
	{ "cdce937", CDCE937 },
	{ "cdce949", CDCE949 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, cdce925_id);

static const struct of_device_id clk_cdce925_of_match[] = {
	{ .compatible = "ti,cdce913" },
	{ .compatible = "ti,cdce925" },
	{ .compatible = "ti,cdce937" },
	{ .compatible = "ti,cdce949" },
	{ },
};
MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);

static struct i2c_driver cdce925_driver = {
	.driver = {
		.name = "cdce925",
		.of_match_table = of_match_ptr(clk_cdce925_of_match),
	},
	.probe		= cdce925_probe,
	.id_table	= cdce925_id,
};
module_i2c_driver(cdce925_driver);

MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
MODULE_LICENSE("GPL");