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CDC3S04: Analog and Digital GND seperation

Nir Alon
Intellectual 600 points
Part Number: CDC3S04

Hello all,

By looking at the CDC3S04 pin layout, I can see that there is no clear physical separation between analog and digital pins:

 

If I wish to create a separate analog GND and digital GND in my PCB, how should the separation route be in this case?

Thanks a lot!

Nir

 

  • 0
    TI__Genius 16845 points

    Hi Nir,

    It is recommended to have a constant reference plane under controlled impedance trace. This avoids impedance discontinuities which will impact signal integrity.

    You also want to have decoupling capacitors located very close to the supply pin.

    One way to achieve this is to situate the AGND as a plane extending above pins in rows A, B, and C. DGND plane would then extend from row D pins down to row E and below. There are other ways to accomplish it as well if you prefer it to using a single GND for this device.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Intellectual 600 points

    Hi Lane, 

    Thanks for your reply.

    I plan to use 3 clock buffers, the clock request pins are not needed (I'm using I2C interface), and also RESET pin is not needed.

    Under these conditions, will the following solution is acceptable?

    (Decoupling capacitor for DVCC\AVCC will be located at the bottom side)

    Thanks again

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 16845 points

    HI Nir,

    I don't anticipate any issues with it

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Intellectual 600 points

    Hi Lane,

    Thanks!

    One more thing - in your first answer you wrote that "It is recommended to have a constant reference plane under controlled impedance trace"

    Should the clock traces have a controlled impedance?

    If the answer is yes, what is the drivers typical output impedance?

    By the way, in the past someone did ask if the CDC3S04 can drive a 50ohm load:

    https://e2e.ti.com/support/clock-and-timing/f/48/t/704353?tisearch=e2e-sitesearch&keymatch=CDC3S04

    The answer was no, but I can see no loading problem when I connect my CDC3S04EVM to 50ohm spectrom or scope (phase noise remains ok, power supply current remains ok...I'm using the high-drive capability of the device)

    I can't understand why the buffer does not function well under 50ohm load...

    Thanks and best regards,

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 16845 points

    Hi Nir,

    Yes, it is recommended to have the clock traces with impedance controlled to 50ohm.

    I have not tried to used CDC3S04 with 50ohm loads but I would imagine that it is doable. If it is meeting your requirements then I don't anticipate you would have an issue.

    This device is an older part and design support is limited but let me know if you have any additional questions

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Intellectual 600 points

    Hi Lane,

    This is an old part, but a very good one :)

    We will design the board with 50Ω impedance as you recommended.

    We have no further questions for now, thank you very much!

    Nir