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LMX2581: TCXO compatiblity to OSCin

hadi javadi
Prodigy 60 points
Part Number: LMX2581
Other Parts Discussed in Thread: LMK04828

Hello,

In LMX2581 Datasheet, there are below data relevant to OSCin pin:

 - a graph showing the input impedance vs. freq. (mag = 300 - 600 ohm for freq. less than 100 MHz),

 - min. & max. amplitude (0.4 - 1.8 V) of ac-coupled clock, and

 - the acceptable freq. range of clock.

Moreover, two notes are seen as following:

 - higher slew rate leads to better noise performance, and

 - recommendation of external components to make the OSCin impedance 50-ohm.

However, I am not able to choose the proper TCXO as the clock maker. Let me ask:

 - Which output kind of TCXO should I consider, e.g. CMOS, 10kOhm || 10pF, ECL, LVDS ...?

 - Why the aforementioned 50-ohm impedance is recommended?

 - Suppose I select a TCXO with Vs = 1.8V, OL = 10kOhm || 10pF, Waveform = Square and ac-coupled it via a series resistance of 200-800 Ohm to OSCin. What would be the problems, if any?

Thanks in advance to anybody who reply to me.

  • 0
    TI__Guru* 81510 points

    Hi hadi,

    The slew rate of the reference clock will affect the PLL noise, but this is frequency and format dependent.

    For example, at 10MHz, definitely, a square wave has much better slew rate than a sine or clipped-sine wave. However, at 100MHz, the slew rate difference becomes not significant. 

    LMX2581 suggests 50Ω OSCin because this will return less spurs in fractional channels. 

    A typical TCXO has only 1Vpp clipped-sine wave output, it is not able to drive a 50Ω load. If you can source a CMOS output TCXO, then you can enjoy the high slew rate benefit and at the same time, you can make OSCin 50Ω with external shunt resistor. 

    With clipped-sine wave TCXO, we can simply AC-couple it to OSCin, 

  • 0 in reply to Noel Fung
    Prodigy 60 points

    Hello Noel,

    thanks for your good reply.

    after you said, I found out from datasheet that signal integrity and the impedance close to 50-ohm was recommended as one of the methods to reduce "integer boundary" spurs.

    However, It seems this is not followed by TI's own reference design . In that design, OSCin pin is fed by an LVPECL output of LMK04828, neglecting any 50-ohm.  Would you please confirm or reject this or any additional comment to this, e.g. spur level degradation due to omitting 50-ohm, if you know or can guess? Does it reflect that 50-ohm is not so important? Moreover, PLLatinum does not include such recommendation in LMX2581 design tips.

    anyway, let me assume that 50-ohm is inevitable. Is there any cost -effective way to buffer a non-CMOS TCXO output to drive such a low-impedance load to a proper level? If I use an emitter-follower BJT with high fT parameter, does it work well?

    with regards,

  • 0 in reply to hadi javadi
    TI__Guru* 81510 points

    Hi Hadi,

    I agree that the reference design circuit was not optimized. Anyway, back to your system. What is the frequency of your TCXO?

  • 0 in reply to Noel Fung
    Prodigy 60 points

    Hi Noel,

    thanks for reply.

    I want to get a fixed frequency L/C-band LO from LMX2581 to inject to a down-converting mixer. As PLLatinum spur tips, higher slew rate but lower amplitude reference input would be better. similar tip can be seen for phase noise. Note that nothing related to 50-ohm OScin pin is clarified. My present step is selecting a proper oscillator compatible to LMX2581 among wide variety of parts. Maybe, the clear selection, would be one has been used in EV. Modudle, i.e. CWX813-100.0M in the same circuitry as EVM. But, I wonder if a smaller, cheaper yet better in phase-noise one, e.g. ASTXR-12-38.400MHz, would be compatible?

    with regards,

  • 0 in reply to hadi javadi
    TI__Guru* 81510 points

    Hi hadi,

    With reference clock frequency = 38.4MHz, what are the output frequencies? 

    If the output frequencies are integer multiple of 38.4MHz, you don't need to worry spurs. However, this TCXO output format is clipped-sine wave, maybe the phase noise cannot be optimized. 

  • 0 in reply to Noel Fung
    Prodigy 60 points

    Hi Noel,

    I will try to check the spur level in both integer and fractional modes later when it is operational to set the proper one beside other constraints in my project.

    returning back to the TCXO compatibility:

    1. I saw no explicit formula relating pll closed-loop phase noise to osc. slew-rate to address wave-format. do you have any explicit one?

    2. according to CWX813-100.0M (XO used in EvM) datasheet, how can one find this CMOS XO can be loaded by a 50-ohm impedance? I know this load is used for signal-integrity regarding higher harmonics and in in a voltage-dividing way to limit Vosc. There is a CMOS TCXO with better stability, i.e. ECS-TXO-2520-33-400, I want to know whether I can substitute the previous one with it?

    thsnks again.

  • 0 in reply to hadi javadi
    TI__Guru* 81510 points

    Hi Hadi,

    1. No, we don't have formula on pll phase noise vs slew rate.

    2. All or most of the CMOS XO are able to drive 50ohm load. However, the output voltage will drop because of the huge amount of current drawn. This is not an expected use case for the XO, so you would not find this information in the XO datasheet. 

    The ECS TCXO looks good.

  • 0 in reply to Noel Fung
    Prodigy 60 points

    Hi Noel,

    Thanks for constructive reply.

    1. there is an item in XO's specifications indicating max. current consumption, ~30mA and ~6mA for CW's and ECS's above XO, respectively. Is it there to determine how much voltage at max. would be across 50-ohm load? If so, then it should be greater than min Vsco. Shouldn't it?

    2. In EvM there are separated grounds for XO and LMX2581 connected to each other by a ferrite bead to provide isolation, a way that is NOT followed by TI's own reference design, the other one. The ferrite bead seems to cause more impedance on Vsco to be sensed by LMX. Is it included in voltage dividing ratio? Doesn't it affect the signal integrity and slew-rate on osc. pin?

  • 0 in reply to hadi javadi
    TI__Guru* 81510 points

    Hi hadi,

    1. For details, I think you'd better ask the XO vendor. What we usually see is its voltage drop but it is still able to provide stable output clock to drive 50Ω load.

    2. The EVM was developed with flexibility to support different testings, so the GND are separated. In reality, we can combine all the GND into a single ground.

  • 0 in reply to Noel Fung
    Prodigy 60 points

    Hi Noel,

    maybe the final question in this thread.

    the output of XO is usually a half duty cycle pulse-form voltage with approximate low and high level between 0 and 3.3 Vdc, respectively, for the above XOs. Isn't it? however, the ac-coupling capacitor is located after the RES-pad right close to osc. pin, while it could be located before RES-pad to reduce the current load and power drag on XO. Would you please comment on this? Moreover, Is there any Vdc on osc. pin due to internal circuitry of LMX2581?

  • 0 in reply to hadi javadi
    TI__Guru* 81510 points

    Hi hadi,

    Here is the correct connection.

    XO output  --> AC-coupling cap --> 50Ω shunt --> AC-coupling cap --> OSCin of LMX2581.