WEBENCH® Tools/LMK04610: Compute settings instead Clock Architect

Tool/software: WEBENCH® Design Tools

Hi,

probably noticed that Clock Architect is not working anymore.

Unfortunatelly LMK04610 is not defined in Clock Design Tool nor in CodeLoader 4!
Is there some work in progress at TI side to help designers with this part or do I have to do all computations manually from datasheet?

I need to generate few signals all phase synchronized:

1. 4x 1000 MHz (or alternatively 1500MHz in future)
2. 4x 3.125 MHz as SysRef signal for JESD204B
3. 100 MHz
4. 300 MHz
5. 100 MHz after power-up to clock FPGA. It will then configure LMK04610 by SPI.

I expected to use:

• LMK62I0-100M as a 100MHz CLKIN0 of LMK04610
• CVHD-950-100.000 as a 100MHz VCXO
• PLL2 frequency = 3000 MHz
• Dividers for individual channels will be:
  1. 3
  2. 1280
  3. 30
  4. 10
  5. OSCout

But then there are lot of registers with no guideline what value to put in. For example:

10.2.2.1 PLL Loop Filter Design
Contact TI with the application requirements to get the optimized loop filter settings.

Please help