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TPL5010-Q1: Schematic Review

Part Number: TPL5010-Q1

Hi,

Please could I ask for one of the apps team to review this schematic and provide feedback on any changes?

The main idea is to have delay logic with the simple time set - I can share more detials 1-1 if needed.

Ross

  • Hi Ross,

    The 10K pullup on RSTn pin is connected to a different supply than VDD, which can be problematic if both supplies aren't operating at the same time. One potential concern is that it may be possible for the transistor logic in the center of the schematic forces RSTn to GND while the device is trying to drive RSTn output high.

    Kind regards,
    Lane

  • Hi Lane,

    Yes, you're correct. Power rails are not operating at the same time.

    First comes and non-interruptible is P_SMPS_MAIN_3V3, and the P_SMPS_QC_3V3 is controlled by the Router Processor.

    The initial state of the latch is set by the ~DI_RP_MAIN_SMPS_3V3_PG~ that is , by the way, the global reset signal and has the Highest priority. Thus, we may exclude central transistor logic from the consideration.

    Does this sound ok?

    Ross

  • Hi Ross,

    Thanks for the information. Based on this power sequence, there will be a moment when the input voltage on the RSTn pin is greater than VCC which violates the input voltage spec in the absolute maximum ratings. If the transistor circuit is already driving the pin low, or if the pullup is pulled to the same rail as the device’s supply, it should be fine.

    Kind regards,
    Lane