LMK03806: Options for generating <1MHz clocks (I2S LRCLK)

Hi Pavel,

Thank you for your question. I would like to circle back with the team to confirm some things before I provide you with an answer. Please give me a few days.

In the mean time, could you help clarify something for me? From my understanding it sounds like you want to provide a 36.864 MHz reference input to a chip and have it divide to two different clocks where one can range from 48 kHz to 768 kHz and another can range from 2.304 MHz to 36.864 MHz, is this correct?

Regards,

Adam

Hi Adam,

I very much appreciate your help. I tried to find everything in the TI's Clock Design Tool but some of the chips were not there.

Actually I found a mistake in my plan for a particular DAC/ADC and will have to find new candidates - figuring out the final clock combination will take me a few days. Please can you wait with asking your team a bit until I get all the frequencies?

Thanks a lot.

Best regards,

Pavel.

Yes of course, Pavel. You can respond to this thread when you've chosen your new frequencies.

Best of luck,

Adam

Hi Adam,

This is the frequency plan:

Background:

* frequency group 1 is for multiples of 48kHz audio samplerate + 512kHz

* frequency group 2 for multiples of 44.1kHz audio samplerate

* Either two crystals (i.e. a solution with two inputs) or crystal for group 1 and internally PPLed for group 2

The two groups have same dividers, just different "input" clock

Group 1:

Group 2:

The largest divider is 1:768.

The dividers for 512kHz could be simplified if the 32.768 clock were precisely PLLed from 36.864. Or it could be the other way round, using 32.768MHz crystal (a standard and common value), and the 36.864MHz could be PLLed.

Thank you very much with your help with TI products for this solution.

Best regards,

Pavel.

Hi Pavel,

Thanks for returning to this thread with an update. I'll need a couple days to review this to make sure I can provide you with the correct answer. I'll circle back by the end of the week.

Best,

Adam

Adam, thank you for your help, great customer-oriented approach by you and TI.

Best regards,

Pavel.

Hi Lane,

Thank you for your recommendation.

I apologize if my description of the frequencies is misleading. I do not want to generate both group 1 and group 2 freqs at the same time. Always only the four frequencies from one column - DAC and ADC master clocks + I2S signals (bitclock, sample clock). The two groups differ just by the input/main/master frequency, otherwise the dividers are identical (plus the 512kHz-related column in the first group). If the group 1 could be dividers only, and the group 2 were PLLed from the group1 input frequency (or the other way round), that would be fine. Or low-jitter PLL for both groups.

I would like to aim a bit better than the 50ps jitter of PLL1707. The device will be a measurement adapter and I would like to take advantage of the latest low-/ultra-low-jitter clock chips.

Best regards,

Pavel.

Hi Pavel,

CDCE925 has a very low VCO range of 80MHz to 230MHz, and it could not even achieve the frequencies using only the internal dividers, but this device does not have the ultra-low jitter you are looking for. Many ultra-low-jitter devices divide down from higher VCO frequencies in the GHz. I think you will want to use a high performance PLL with a high performance external divider that has sufficient depth.

CDCE6214-Q1 might work here. Set the VCO to 2335.536MHz, PSA = 4, and Chx_div = 1655 to hit 352.8kHz. To hit 512kHz + 384kHz, you will need to change the VCO frequency to 2340.864MHz, PSA = 4, and chx_div = 1143 and 1524. Alternative VCO frequencies are possible.

If this is an option, you might need two reference clocks to source the different VCO frequencies, if the fractional divider cannot hit both frequencies exactly. Fractional peformance may be slightly degraded in comparison to integer. CDCE6214-Q1 can accept two reference clocks, but only one XTAL.

Kind regards,
Lane

Hi Lane,

Thank you very much for your help. CDCE6214-Q1 is a very handy chip. I looked at the equations at https://e2e.ti.com/blogs_/b/analogwire/archive/2014/07/31/clocking-sampled-systems-to-minimize-jitter

When entering 16.384MHz and 2ps jitter for LVCMOS and fractional ratio, I get 103dB SNR. Plus 32x oversampling for 512kHz samplerate, i.e. 2^5, i.e. 5 * 3 dB = +15dB => 118dB SNR at 512kHz. Really I am not sure I calculate that correctly.

From the jitter POW only the master clocks are critical, the other clocks must be only synchronous. Plus, I need the BCLK as tri-state for some other reason (easy to solve with a simple buffer chip though).

Lane, please can you comment on this:

The ultra-low-jitter LMK03806 (the best jitter chip from TI, if I understand correctly) goes only down to 2.37GHz min VCO / 1045 max divider = 2.268MHz. My slowest BCLK is 2.1168MHz, i.e. a divider by 2 would be required anyway. How about using 100MHz octal flip/flop SN74LVC374A-Q1 with 3-state outputs for generating the BCLK (1 flip/flop :2, i.e. input range would be from 4.2336 to 49.152MHz) and the LRCLK (6 flip/flops :64, i.e. input range would be from 2.8224 to 32.768MHz). That would move all the frequencies to ranges within LMK03806 reach. SN74LVC374A-Q1 is very inexpensive.

Please would there perhaps be a better suited chip than LMK03806 (perhaps cheaper, or easier to implement/fewer outputs, etc.) for the task if fast external flip/flops were used for the LRCLK (resp. also BCLK)?

I very much appreciate your help. Finding proper clocking scheme is actually quite a complicated task :-)

Best regards,

Pavel.

Lane, thanks a lot for your kind help. I will continue my search in that direction.

Best regards,

Pavel.