LMK04616: LMK04616ZCRT

Hello Moti,

I reviewed the data, and we don't have specific numbers for zero-delay using CLKin0 instead of OSCin for the PLL2 zero-delay setup. However, we do know the difference in CLKin-to-CLKout and OSCin-to-CLKout propagation delay when in distribution mode. Since the only difference between CLKin/OSCin delay is in the path leading up to the source selection mux for downstream circuitry, the delay difference should be representative of the difference when PLL2 is used.

OSCin-to-CLKout propagation delay is around 3.35ns at nominal PVT, whereas CLKin-to-CLKout propagation delay is around 2.25ns at nominal PVT. So my expectation is that the CLKin to CLKout propagation delay would be about 1ns less than OSCin-to-CLKout propagation delay.

Regards,

Hi Derek

Thank you for your quick answer.

If I understand your answer correctly, the zero-delay relat to the selected input clock.

So, if I select CLKinX or OSCin, at zero-delay the phase between the selected input clock and output clock will be near 0nS.

Is it true?

Regards

Moti Cohen

DSIT

Hi Moti,

That is the idea, yes. In principle, at zero-delay the phase between the selected input clock and output clock will be near 0ns. In practice, there are some differences in the input buffer structure, the output buffer structure, and some of the divider structure which cause the actual phase offset to be slightly off from 0ns; but it is tuned to be close to 0ns.

It is also important to note that the phase between the input and output clocks is measured at the phase detector. This means that if the R-divider and N-divider are used (that is, if the phase detector is lower frequency than the input), then there will be R potential phases that could exist between input and output clock. So for example, with 122.88MHz input, 122.88MHz output, and 61.44MHz phase detector, there could be two possible phases that are valid (0° and 180°). Normally during the startup procedure, the R-divider, N-divider, and output dividers are all synchronized so that the phase alignment between input and output is set at 0°. But it is possible for the phase offset to be different, like if the reference input clock is missing for a few cycles and the PLL loses lock.

Regards,