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LMK04826BEVM: LMK04826b configuration using external clock source oscin

Part Number: LMK04826BEVM
Other Parts Discussed in Thread: LMK04826, LMK04832, LMK04828, PLLATINUMSIM-SW

hello

we are using LMK04826B  in one of our application. so i want to configure the LMK by giving 100MHz external source to oscin .

1). I tired configuring LMK in single loop mode by  setting oscin source as independant  ,feeding single ended clock of 100MHz (1Vpp -sine wave/square wave) and output are recorded but if i remove the clock  source the output are present and i  programmed  LMK with same congiuration reg value  without clock source input  then also the output are recorded.  so how can we  justify that  input source  has an effect on output clock that are being generated?

2)i tired configuring LMK in dual loop mode by giving same input to clockin and observed the same result as( I)

3) how to Configure lmk using external clock source for oscin and clkin single ended input  ?

4)can i configure LMK in dual loop mode by giving clock input to OSCIN ?

note :the above experiment has been carried on lmk04826B evm board and i hav attached the config file for single loop .

single_loop_config.txt
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010008
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010402
R261	0x010500
R262	0x0106F1
R263	0x010711
R264	0x010814
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C02
R269	0x010D00
R270	0x010EF1
R271	0x010F05
R272	0x011008
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F9
R279	0x011700
R280	0x011818
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF1
R287	0x011F33
R288	0x012008
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012700
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013733
R312	0x013825
R313	0x013900
R314	0x013A0C
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01408F
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x014400
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016108
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x016508
R369	0x0171AA
R370	0x017202
R380	0x017C18
R381	0x017D77
R358	0x016600
R359	0x016700
R360	0x016864
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

 

  • Hello,

    USER118 said:
    1). I tired configuring LMK in single loop mode by  setting oscin source as independant  ,feeding single ended clock of 100MHz (1Vpp -sine wave/square wave) and output are recorded but if i remove the clock  source the output are present and i  programmed  LMK with same congiuration reg value  without clock source input  then also the output are recorded.  so how can we  justify that  input source  has an effect on output clock that are being generated?


    What are you using to record the information?  Is it an E5052 or similar phase noise analyzer?

    USER118 said:
    4)can i configure LMK in dual loop mode by giving clock input to OSCIN ?


    No.  Not in any traditional use dual loop use case.  However you could technically run PLL1 and PLL2 in parallel (not in series as is the dual loop jitter cleaning mode) if you input to OSCin as you propose.  You would then connect PLL1 charge pump output to loop filter, then VCO/VCXO, then into CLKinX.  Now you are basically running PLL1 backward with CLKin having the feedback path as opposed to OSCin.  PLL2 could operate in the traditional fashion.  The EVM is not setup for this.

    USER118 said:
    2)i tired configuring LMK in dual loop mode by giving same input to clocking and observed the same result as( I)


    The EVM has a 122.88 MHz VCXO.  I expect the configuration would have to be significantly different or did you replace the onboard VCXO?

    USER118 said:

    2)i tired configuring LMK in dual loop mode by giving same input to clockin and observed the same result as( I)

    3) how to Configure lmk using external clock source for oscin and clkin single ended input  ?

    I'm observing in your configuration that you accept the 100 MHz, divide-by-8 to 12.5 MHz phase detector frequency then multiple up to 2500 MHz for VCO2.  This is not optimal, you should keep the phase detector frequency at 100 MHz.  Then use N prescaler = 5 and N divider = 5 to provide the 100 MHz * 25 = 2500 MHz for VCO frequency.

    This is my recommendation.  The LMK04832 is a very similar and pin compatible device and also covers 2500 MHz with one of it's VCOs.  The LMK04832 TICS Pro profile also has a frequency planner.  Use the frequency planner in the LMK04832 to generate the proper divider configuration for your system, then you configure the LMK04826 in the same fashion.

    Second, to see more about the behavior / output phase noise.  Please download the PLLatinum sim software (PLLATINUMSIM-SW).  You can use the LMK04828 profile to simulate the phase noise output of the LMK04826, this tool does only one loop at a time, for dual loop, you can simulate PLL1, then save that output and load as the input for PLL2.  For your single loop case you can use the noise profile of your 100 MHz oscillator as input and then in the phase noise simulation see what is dominating the noise, the LMK or the 100 MHz noise.

    73,
    Timothy

  • Hie Timothy

    Thank u for ur detail explanation sir

    Sorry for my wrong presentation.

    Record means i can observe the output on the oscilloscope sir and i hav removed the  on board 112.88 Mhz crystal (Lmk02826b evm)To make sure there is no leakage or confusion  and feeding 100MHz from signal generator  to Oscin in single loop mode.

    i hav tired with ur recommendation and result are optimal but the problem still persist as mentioned above in point 1.the same problem is explained below briefly

    case 1: input from signal genrator (100MHz ) to oscin -- output set to 125 Mhz - - configured in single loop mode -- observed output frequency 125Mhz on oscilloscope.

    case 2 NO input from signal generator --- output set to 125 Mhz - - configured in single loop mode -- observed output frequency 125Mhz on oscilloscope.  why?

    lmk is producing output without any input .why?

  • Hello,

    Using an oscilloscope you would not be able to tell the differences in performance using the different methods.  You would need a phase noise analyzer.

    USER118 said:
    case 1: input from signal genrator (100MHz ) to oscin -- output set to 125 Mhz - - configured in single loop mode -- observed output frequency 125Mhz on oscilloscope.


    In case 1, after locking to 2500 MHz from 100 MHz reference, you can...
    (1) observe the PLL2 digital lock detect by programming PLL2 DLD output for either the Status_LD1 or Status_LD2 pin.
    (2) measure the CPout2 voltage, it should be center rail.
    (3) measure the output with a frequency counter referenced to your signal generator.  You will measure exactly the 125 MHz.

    When changing to case 2, if you simply unplug the 100 MHz reference...
    (1) the PLL2 DLD should go low
    (2) the CPout2 voltage should rail.
    (3) The output frequency should change about 1 MHz off.

    Now you would still receive an output signal and it would be fairly close to the output frequency because during lock and calibration the VCO selects a 'bank' to operate in.  Once in the bank it will stay in that bank after lock.

    If you re-lock the PLL by programming the PLL2 N value again.  (Or simply press Ctrl+L to re-program all the registers again).  I expect you will see a frequency further off from 125 MHz that simply removing reference from case 1 --> case 2.

    The LMK0482x does not have a muting function to turn outputs off if the reference is lost and the internal VCO will still oscillate even if there is no input reference.

    73,
    Timothy

  • Hie timothy

    Thanks for the detail explanation. Appreciate it

    my issued is resloved On my board but not on EVM

    1.Pll2 dint got locked in EVM

    2.The holdover feature which u hav suggested last for how much time?

    Can we disable that feature? How does this effect the performance