LMK04616: Question about SYSREF timing

Hi Jonathan,

Think of the SYSREF pulser as just a MUTE function applied to the channel divider.

100MHz case:

1. SYSREF duration is logic high for 5ns (half of 100MHz period).
2. Varies depending on SYSREF frequency. Looks like about 6 SYSREF periods based on https://www.ti.com/lit/an/snau222/snau222.pdf figure 30, but I don't know if they matched the delay on all the measurement lines in that app note so I'm not sure. Either way, the timing is calculable and repeatable
3. Deterministic, SYSREF_REQUEST is reclocked to channel divider and takes some number of CLKout cycles to propagate through the output (looks like 6).
4. n/a

100MHz on one channel, 50MHz on another channel:

1. Theoretically yes, if you know the phase of the SYSREF divider for each output at the instant the SYNC signal is received. Because CLKout1 and CLKout2 are at different frequencies, the SYSREFs will occur at different times; it will take about double the time for the 50MHz pulse to appear.
2. Not necessarily. There are two cycles of the 100MHz clock which could trigger the same 50MHz clock edge. If you send the SYNC signal at the same phase with respect to the lowest frequency SYSREF each time you make the SYSREF request, you should have repeatable results. Note also that there's some slight path matching differences in the SYSREF_REQUEST path inside each device, so there's some edge case where setup time violations could cause an off-by-1 error. The above-linked app note shows an example of this setup time violation in figure 32, and there's another example below.
3. n/a (explained in 2)

Also, here's an image that shows what happens in your second example, with timebase set to 20ns so each div is one period of 50MHz clock. I matched the trace lengths for the SYSREF pulse and the SYNC monitor signal, and you can see that triggering on the 50MHz SYSREF shows two things:

1. It takes 6 SYSREF periods (divs) to retime the SYNC signal to the SYSREF clock
2. If the phase of the SYNC isn't exact with respect to the lowest SYSREF frequency, there's some possibility of off-by-1 pulses on higher frequencies. Considering the propagation delay through the dividers in terms of VCO post-divider clock cycles will be different depending on the divider settings, the phase will need to be carefully controlled to ensure consistent pulses

To prove that consistent pulse timings are achievable, here's what happens when the SYNC signal is locked and aligned to the SYSREF phase:

Regards,