CDCM6208V1EVM: Gate the clock outputs and timing

patrick nefos

Part Number: CDCM6208V1EVM
Other Parts Discussed in Thread: CDCM6208

One more question. Is it possible to gate (turn off then re-enable the (4) 100 MHz) Y0-Y3. What is the time from enable to valid clock? - Thanks, Patrick

over 3 years ago

0 Shawn Han over 3 years ago

TI__Genius 9920 points

Method 1, Register control output type with Disable.

Have to control one channel by one channel. Most of latencies are on register operations.

Method 2, Reset by pin. Turn off all output in reset.

VCO need be calibrated again, PLL need relock again. Most of latency depends on PLL lock time.

Method 3, By SYNCN pin. Turn off all outputs in synchronizing.

"The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the
SYNC pin assertion." Refer to details in CDCM6208 datasheet 9.2.2.9 Output Synchronization.

0 patrick nefos over 3 years ago in reply to Shawn Han

Expert 1760 points

Can you give timing estimate for Method 1?

0 Shawn Han over 3 years ago in reply to patrick nefos

TI__Genius 9920 points

For example,

I2C clock max 400kHz, SPI clock max 20 MHz.

One register write need 32 bits operation.

Now you can estimate the timing for a register operation.

After the register is available, on/off an output is in several ns level.

Clock & timing

Clock & timing forum

CDCM6208V1EVM: Gate the clock outputs and timing