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LMX2595: SYNCing multiple devices

Tony Rohlev
Prodigy 230 points
Part Number: LMX2595
Other Parts Discussed in Thread: MSP430F247, SN74AUP2G79, LMX2594EVM

Hello again,

My new question is about synchronizing multiple LMX2595's that are driven by the same OSCin signal and how to know if the synchronization procedure was successful. Specifically, this is in regard to a 'Category 3' SYNC event as defined in Figure 33. of the data sheet and the ensuing 'Procedure for Using SYNC'.

Below are the particulars of the design:

OSCin frequency: 100 MHz (OCXO generated sine wave)
Number of LMX9595's using the same OSCin input signal to be synchronize: 8
SYNC pin used: Yes

Hardware driving SYNC pin: A portion of the OSCin signal is sampled, prior to its splitting and distribution, and converted from a sine wave into two complimentary CMOS outputs with a LTC6957-4 buffer. The two complimentary outputs have a typical skew of 120 ps (~1.2% of a cycle) and care is taken to not further degrade that. These CMOS signals are then used as the clock inputs of two separate D-type flip-flops (SN74AUP2G79) whose Data inputs are tied together and driven by the system micro-controller (MSP430F247). The Q outputs of the two flip-flops go into a 2:1 multiplexer (NC7SV157) whose Select input is again driven my the micro-controller and whose output drives all 8 SYNC pins through traces that are length matched to +/-50 ps.

Synchronization strategy: The hardware described above generates two rising edges. The first is at a fixed delay from the rising edge of the 100 MHz OSCin clock, the second, at approximately the same fixed delay, from the falling edge of the OSCin clock. The micro-controller is used to choose which of these two signals drives the SYNC pins of the LMX2595's. If a 'Category 3' SYNC event is called for and the rising edge signal does not synchronize the PLL's for what ever reason, then a SYNC can be attempted again with the falling edge signal. The signals are separated by approximately half a cycle of the OSCin frequency, 5 ns in this case, so there is a small chance they both work, but if one doesn't then the other should.

My question is: Short of physically monitoring the output phase of the 8 LMX2595's in the system (a decidedly non-trivial task at 20 GHz) is there anyway of verifying if the 'Category 3' SYNC event generated from one edge of the hardware above produced the required synchronization or if the other edge should be used?

Thank you,
Tony

  • 0
    TI__Mastermind 27881 points

    Tony,

    There is no "Sync Complete" bit or pin for this.

    That being said, recall that there is MASH_RST_COUNT.  When this timer runs out, the SYNC should be complete.

    Now if you want to check the SYNC, there is no other way than looking at the outputs.

    Also realize that this device has very fine phase adjustment and deterministic phase.  However, deterministic phase does not mean that every device has the exact same propogation delay, but rather that this delay can be made deterministic between power cycles.  Then any phase differences between the devices can be tuned out with the MASH_SEED field.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 230 points

    Hello Dean,

    I think I understand, but let me confirm...

    The question is: Given the Setup and Hold time requirements of the SYNC pin relative to the OSCin edge (2.5 and 2.0 ns respectively), and given that the maximum OSCin frequency is being used (100 MHz) with the minimum cycle time (10 ns), there is good chance that a rising edge on the SYNC pin will not initiate the synchronization sequence in the device. In this case the rising edge of the SYNC pulse should be delayed or advanced and the procedure tried again.

    The LMX2595 can not communicate the successful initiation of a SYNC procedure over the SPI bus. However, the timing of the SYNC pulse is only critical when fractional mode is being used, in which case the MASH_RST _COUNT should also be in use. The sum of the MASH_RST_COUNT and the VCO calibration time gives an ideal of approximately how long it takes, after a successful SYNC initiation, for the phase of the individual devices to align with each other.

    The synchronization procedure after a power or frequency reprogramming cycle might then be:

    1: Observe the output phase of each device (if you can).
    2: Initiate a rising edge on the SYNC pins.
    3: Wait the for an amount of time grater than the sum of the MASH_RST_COUNT and VCO calibration time.
    4: Observe the phase of each device again.
    5: If the phases moved, the procedure was successful. If not, then repeat it with a delayed/advanced SYNC edge.

    This assumes that each OSCin path, as well as each SYNC signal path, are fairly well matched in delay to the individual devices.

    After a successful SYNC procedure the MASH_SEED word can be used to zero out any remaining phase difference between the devices.

    Will that work?

    All the best,
    Tony

  • 0 in reply to Tony Rohlev
    TI__Guru* 97720 points

    Hi Tony,

    Yes, the sequence is correct.

    One point to clarify, fractional channel is definitely requires Cat.3 SYNC. But it is possible that an integer channel will also requires Cat.3 SYNC. Check the flow chart in the datasheet for details. You could verify the sync category with the help of TICS Pro. 

    The SYNC pulse timing is very critical, I have seen in my lab that when I was attempting to sync two LMX2594EVM, I was not able to get them sync because of poor wiring.