LMK04816: Loop Bandwidth

Joe Suat Chai

Part Number: LMK04816
Other Parts Discussed in Thread: PLLATINUMSIM-SW

From LMK04816 datasheet:

1. PLL1 typically uses a narrow loop bandwidth (10 to 200 Hz) to:

- retain frequency accuracy of external reference clock

- suppress high offset frequency phase noise (I suppose it means suppress high frequency phase noise from external reference input? or noise source from PLL1 or external VCXO?)

2. PLL2 can operate with a wide loop bandwidth (50k to 200kHz) to:

- take advantage of superior high offset frequency phase noise of internal VCO

But from TI's Clock Conditioner Owner’s Manual (SNAA103), the loop bandwidth is at the crossover frequency of unshaped PLL noise and free-running VCO noise in order to minimized Integrated phase noise:

So here's the question, if the PLL noise is unchanged but VCO noise improve (in the case of LMK04816 PLL2 internal VCO), wouldn't the crossover frequency become smaller (shift to the left)?

Then how can PLL2 which operate with a wider loop bandwidth take advantage of superior high offset frequency phase noise of internal VCO since the phase noise is now dominated by PLL noise at high frequency with wider loop bandwidth?

over 4 years ago

0 Noel Fung over 4 years ago

TI__Guru* 89050 points

Hi Joe,

1. it means suppress high offset frequency phase noise from external reference input. Loop filter is a low pass filter to the reference clock and PLL, but it is a high pass filter to the VCO.

2. If VCO phase noise gets better, the crossover frequency will shift to the left and as a result, we don't need very wide loop bandwidth. Just like PLL1 with an excellent phase noise VCXO, the loop bandwidth should be small.

0 Joe Suat Chai over 4 years ago in reply to Noel Fung

Prodigy 250 points

Hi Noel,

Since internal VCO for PLL2 have superior phase noise, then we shouldn't need wide loop bandwidth for PLL2, but why datasheet still recommend for wider loop bandwidth (50k to 200kHz) as compared to PLL1 (10 to 200Hz)?

0 Noel Fung over 4 years ago in reply to Joe Suat Chai

TI__Guru* 89050 points

Hi Joe,

The VCO is constructed with LC-resonator, phase noise is much poor than the crystal-based VCXO.

Here are the phase noise from PLL2, VCXO and VCO, they are scaled to the same frequency.

as you can see, the crossover between VCO and PLL2 is around 200kHz. If we set the loop filter to 200kHz (the Total trace), we can enjoy low PLL noise at low offset and low VCO noise at high offset.

If the VCO had the same phase noise as the VCXO, the appropriate loop bandwidth should be 10kHz.

0 Joe Suat Chai over 4 years ago in reply to Noel Fung

Prodigy 250 points

Hi Noel,

I think I understand above now. Thanks.

By the way, I have another question regarding the closed loop transfer function with second order loop filter.

By referring to TI's Clock Conditioner Owner’s Manual (SNAA103):

Which is still valid for T1 and T2.

However, when it comes to further derivation, the result doesn't seem to tally with simulation:

I suppose simulation is more accurate?

I wonder if you can help to further derive on equation 3.18 and 3.19? Or is there any document which I can refer for further understanding?

My application of LMK04816 involve 0-delay Mode with external feedback, thus understanding the transfer function can ease in choosing correct value of C1, C2 and R2 because the Loop Bandwidth seems to be in reciprocal relation with feedback counter, N:

0 Noel Fung over 4 years ago in reply to Joe Suat Chai

TI__Guru* 89050 points

Hi Joe,

For the equations, please read Dean's book. I think you can rely on the simulation tool, which we have been using for more than 10 years.

0 Joe Suat Chai over 4 years ago in reply to Noel Fung

Prodigy 250 points

Hi Noel,

Thanks for the Dean's book,

The ωC and φ should be in radian, the equations match with simulation now.

I know I can rely on simulation tool, just that I want to understand the concept behind.

Thanks again.

0 Joe Suat Chai over 4 years ago in reply to Noel Fung

Prodigy 250 points

Hi Noel,

I have another question regarding the LMK04816 loop BW.

For the typical PLL closed loop where the feedback to phase detector is from VCO output and through N denominator:

We know that

Forward Transfer function, G(s)= (ICP.KVCO.Z(S))/S

Feedback Transfer function, H(s)= 1/(N)

| 1 + G(jω)H(jω) | = 0 ; Loop BW = ω/2π

And the result is able to verify with TI Clock Design Tool.

However, for the 0-Delay Dual Loop Mode below:

The feedback to first PLL is from output of second PLL.

So the Feedback Transfer function of First PLL become:

H(s)= Closed-Loop Transfer Function of Second PLL/N

Which is no longer able to simulate with TI Clock Design Tool.

Is there a way to know and verify the BW of first PLL in 0-Delay Dual Loop Mode?

And how is the BW affecting the locking and phase noise in this 0-Delay Dual Loop Mode?

Thanks.

0 Dean Banerjee over 4 years ago in reply to Joe Suat Chai

TI__Mastermind 27661 points

Hi,

For the 0-delay mode, the channel divide (D) gets put in series with the N divider value (N), so the effective feedback divide is D*N

This does make the loop bandwidth narrower and unoptimized. So when you design, you should put the product N*D for the clock design tool.

We also have the PLLatinum Sim tool (ti.com/tool/PLLATINUMSIM-SW). This has a more powerful loop filter designer on it. I didn't see the LMK04816 tool there, but you can modify the VCO gain, charge pump gain, and feedback divider value to whatever you want them to be.

Regards,

Dean