Hello,
Could you please suggest suitable frequency modulation scheme to get the modulated output at the LMX2694 PLL chip output with below configuration.
- PLL operating Mode: Fixed Frequency
- Carrier Freq: 7.000 GHz
- PFD Frequency: 20MHz
- N Divider: 700
- Loop BW: 50 kHz
- Modulation Freq range: 30Hz to 1200Hz (Tunable and Fixed at given point of time)
- Modulation Depth range: 30Hz -1500Hz (Tunable and Fixed at given point of time)
As shown in the above Fig, there are 3-ways (@ Refclk, @PLL and @VCO) to get the modulated output at the high frequency carrier signal and
With modulation input of 500Hz @ Refclk(10MHz) the modulation depth/deviation at carrier modulated output@7GHz multiplied by N divider value of 700.So to produce the modulation depth of 500Hz @7GHz, need to apply very low frequency modulation depth of around 0.7Hz(500Hz/700(N-div)) which is difficult to product such low frequencies.
Could you please suggest the suitable solution to resolve the issue with applying modulation signal either at the PLL side (using Digital Scheme) or at the VCO Vtune side(using Analog scheme using summing of the loop filter output with modulation input).
Regards,
RVP