CDCS501: Could CDCS501 provide the stable 100MHz CLK output?

George Liu1

Intellectual 1570 points

Part Number: CDCS501
Other Parts Discussed in Thread: CDCE913

Hi Sir,

Our customer got a simple application that they would need our CDCS501 to provide the stable 100MHz CLK output.

Could you please share the reference circuit to achieve it? If so, how about the input range?

Please advise, looking forward to hearing from your comments.

Thanks,

George

over 4 years ago

0 Hao Z over 4 years ago

TI__Mastermind 18070 points

Hi George,

I'm afraid that there isn't any reference schematic, but you can refer to the pin descriptions in the datasheet to understand how to connect the pins. It should be quite straightforward. The input frequency range is 40 to 108MHz.

Regards,
Hao

0 George Liu1 over 4 years ago in reply to Hao Z

TI__Intellectual 1570 points

Hi Hao,

Is CDCS501 more like the buffer not the generator?

Our customer need to re-generate the CLK from input maybe 3.2MHz and output become 100MHz.

If CDCS501 is not suitable for their application, could you please suggest another candidates?

Thanks,

George

0 Hao Z over 4 years ago in reply to George Liu1

TI__Mastermind 18070 points

Hi George,

Yes CDCS501 is a clock buffer with SSC generator. What EE is this and is there a reason why the input frequency is as low as 3.2MHz?

If no noise performance is required then you can recommend CDCE913.

Regards,
Hao

Clock & timing

Clock & timing forum

CDCS501: Could CDCS501 provide the stable 100MHz CLK output?