Could you check the start up time from VDD ramp(S0 pulled up to VDD) to Yx output?
And, could you check the required wait time from VDD ramp to ready I2C access.
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1. I am going to assume that your device is at VDD high - 1.8V and VDDO is also high - 3.3V or 2.5V your questions pertain to the writing of the bits themselves - I2C, correct? In this case, we can calculate the amount of time using 'SDA/SCL Timing Requirements' figure 11 on page 5 in the datasheet (below example: Fast-mode at Max):
Registers = 79
29 cycles to write a byte
time = 1/400KHz = 2.5us
Total I2C Clocking time = Registers x # of cycles x time = 5727.5us = 5.7275ms (fastest speed for all registers writing)
2. Assuming we are at VDD there should be no delay to accessing I2C.
3. About your most recent question, could you expand on this question? Address 0x02[3:2] controls Y1_ST0 disabling or enabling Y1, see page 16 of CDCE949-Q1. Y1 disabled to low is an option but I'm not clear what the question is.
For the first question, what I want to know is not I2C time.
What I want to know is the time from VDD ramp(S0 has VDD pullup, so it goes high at the same time) to Y1 output under the default EEPROM setting. Please assume VDDOUT is ramped at the same time or already stable at 3.3V.
For the third question, What I want to know is whether each outputs can be enabled/disabled by only I2C control, or not.
For example, VDD and VDDOUT are stable, S0=low, then change 0x02[3:2] from 01b(3-state, default) to 10b(low output) or 11b(enabled).
I was able to get this tested earlier than I expected, hope this helps!
1. Looking at VDD Trigger to output of Y1 I am seeing anywhere from 320ms to 370ms. Sorry it took me a while to understand what was needed!
3. The outputs can be enabled/disabled by S0 as well as I2C normally, S1/S2 can also be used for pin control but require a change to the EEPROM - see section "Control Terminal Configuration" on page 10 and 11 for further information.