• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 21 subscribers
  • Views 288 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVD2102: Cross talk

Izik
Expert 1565 points
Part Number: CDCLVD2102

Hello 

Do you have any information about channel to channel cross talk with the part CDCLVD2102?

What do you mean by the spec line:  ΔV/ΔT Input edge rate min. 0.75V/nS

If the input signal rise time is higher than the min. value (slower rise time), will buffer not detect the input signal polarity change? 

Thanks

  • 0
    TI__Mastermind 18070 points

    Hi,

    I'm afraid we don't have any data for the crosstalk between banks. As a general rule, if the difference between the two frequencies to be distributed is less than 20MHz, then two separate buffers should be used.

    This means that the minimum slew rate at the input should be faster than 0.75V/ns.

    Fast input edges (short rise time) will not cause any trouble, but slow input edges might.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Expert 1565 points

    Let me share more details on my application. I intend to use this buffer as a level translator between LVPECL input and LVDS output. The signal is a low frequency strobe, similar to SYSREF. 

    My concern is to prevent false reading, when one clock input is toggled, and the other output may create false readings in the FPGA input, that may be identified as logic '1'. So as long as the cross talk parasitic signal is below the VIH low threshold in the FPGA, there shouldn't be any issue. 

    See the attached drawing:

    Thanks

  • 0 in reply to Izik
    TI__Genius 11900 points

    Hello,

    If you only have one input to CDCLVD2102 enabled at a time, I do not expect this to be an issue, especially if the FPGA VIH and VIL have good limits.

    If you  have both inputs enabled simultaneously you maysee a crosstalk spur on the phase noise, but the output frequency will match the input frequency.

    Thanks,

    Vibhu