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CDCE949-Q1: LVCMOS clock input mode

Part Number: CDCE949-Q1

Hi team,

1) Why the EVM has AC coupling(C4) at the clock input even though it's LVCMOS input?

2) For Xin/CLK-pin on the IBIS model, which XTAL input or LVCMOS input is modeled? My customer want to simulate with LVCMOS input mode.

3) In LVCMOS clock input mode, the load capacitor setting should be set to 0pF? or don't care?


  • Hi Atsushi,

    By default the EVM is using the 27MHz, so the AC-coupled external clock (with placeholders for external bias) is unused. But you're right if the input is in LVCMOS format then there's no need for AC coupling cap.

    To my best knowledge, the IBIS model only describes output characteristics, not including phase noise. So the input signal type/quality is irrelevant.

    The load cap is for the XTAL input. No need to add any cap to ground for the LVCMOS input.


  • Hao-san,

    IBIS is "I/O Buffer Information Specification" and it's not only for output but also input. Customer needs the input characteristics to analyze the input signal reflection or so. And I think it has different impedance/characteristics in XTAL mode or LVCMOS mode.

    So I want to know which mode is modeled in the IBIS model, and want LVCMOS mode version.

    For load cap setting, what I want to know is whether the load cap is automatically disconnected and ignored in LVCMOS mode or need to take care(set 0x00 at 0x05 address).

    Best Regards,

  • Hi Atsushi-san,

    It is difficult, if not impossible, to model the XTAL input. It is not needed either, because XTAL input doesn't require signal integrity analysis. So if the input is ever modeled, it can only be regular input, which is LVCMOS.

    LVCMOS and XTAL inputs require very different buffering/driving circuit. So they're separated from each other. The load cap set for XTAL won't affect the LVCMOS input.