This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCLVC1103 Delay between buffer outputs


We have used CDCLVC1103PWR clock buffer part in our application for clocking out 3 clocks from single clock as input. The clock buffer is powered using 3V power rail. The clock frequency is 25MHz. According to datasheet, the propagation delay is of maximum 2ns and output skew is of maximum 50ps. We are observing a delay of about 120ns between outputs Y0 and Y2. We have probed directly on the output pins(3&5) of the IC. Please check and let us know about what could be the problem and any workaround for this.


  • Hi Saravana,

    I would not expect an output skew on the scale of ~120ns. I recommend first to deskew the oscilloscope channels to each other so that there is no relative time delay between the channels. Also measure directly on the IC input pins. Also, recommended to use a pulse train with low duty cycle for this measurement to clearly align an input edge with the same output edge.

    Kind regards,