CDCE925: Clock availability

Hello Shidara,

The CDCE9xx devices offer 2 different settings of each PLL. This means that 2 different modes can be programmed before use and during use case be changed with control pin configuration update.

*Please note this device is not guaranteed to be glitchless while switching frequencies.*

Q1. These modes are definitely available as required.

Q2. This device needs to have some form of programmability, customer application asks for control pin use and therefore requires EEPROM writing before applying to board.

Q3. Please note ClockPro software generates this setting for you, I recommend setting Mode0 - exporting as a .txt file. Then generating Mode1 setting separately and simply change registers for PLL1_1 and PLL2_1.

If order of Y1, Y2, Y3, Y4, Y5 does not matter ClockPro setting will create these outputs but these can be optimized to exact listed modes above.

This device works fine as long as output glitches during changing frequency are allowed.

Hello Shidara,

Q4, Does output glitch cause all outputs or specific output when changing frequency? Output glitch will be caused by reprogramming of device therefore all outputs using set PLLs will have affect. Even if PLLs are bypassed I could see some glitches as those outputs are reprogrammed.

Q5, How long does it take from mode set to clock output to be stable? PLL locking period is ~10us and programming the device depends on how many registers are changing - please see section 9.3.3 'SDA/SCL Serial Interface' or 9.5 'Programming' in the device datasheet if you are interested on how this is done and 7.8 'Timing Requirements: SDA/SCL' if you would like to calculate this.

Q6, How long does it take to stabilize the output after supplying power? This takes ~820us.

Q7, Is there power sequence restriction? There is no power sequence restriction.

Q8, Is it available to change LVCMOS input frequency slowly in the range of 27MHz ± 100PPM? This device does offer VCXO input and is tunable depending on Vctrl input. I'm not sure why this would be a necessity but PLL could become unlocked depending on PLL configurations.

(Doesn't PLL failure happen?)

Q9, Regarding Iddout , How should the customer refer Iddout value below graph in the datasheet P10? There are 5 outputs on - therefore use the line for 5 outputs as a reference, slight deviation from this line might occur due to the different frequencies. Please note the difference in CDCE949 datasheet attached below:

Hello Shidara,

Q5, How long does it take from mode set to clock output to be stable? This is highly dependent on the ramp rate of their power supply connecting to the control pins. If this were connected to a relay toggling between 0V to 3.3V this would be a fast slew and therefore reach minimum voltage Vi(threshold) sooner than a power supply ramping. The only thing that is changing from control pin settings should be the predefined PLL Mult/Div settings. As we've stated previously PLL locking period is ~10us. 

Q8, Is it available to change LVCMOS input frequency slowly in the range of 27MHz ± 100PPM? This device does offer VCXO input and is tunable depending on Vctrl input. LVCMOS is also available as input. The 'pulling range' is under the 'Recommended Crystal/VCXO Specifications' and therefore assumes a VCXO will be used as Vctrl will change this the Crystal input frequency. An LVCMOS input is an already stable input. Does customer expect to use Vctrl with LVCMOS input?

(Doesn't PLL failure happen?)

Q9, Regarding Iddout , How should the customer refer Iddout value below graph in the datasheet P10? Average freq ≒ 35MHz then should I refer 35MHz Iddout of 5output on line, right? Yes, this is the Iddout. Please keep in mind that this is assuming VDDO of 3.3V and 'NO LOAD' as seen in the graph.

Hopefully this helps!

Hello Shidara-san,

Q8, The customer want to change frequency slightly by changing LVCMOS input frequency in the range of 27MHz ± 100PPM.

       Are there any precautions for such usage? Yes, the PLL could become unstable and therefore lose a stable output. This could stem from the PFD losing a stable reference. Keep the frequency close to the expected input.

Hello Shidara-san,

After internal discussion, if the change is large enough the output frequency would be wrong until the feedback loop settles.

Small changes in input frequency should be tame.