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CDCE913: power on reset

Part Number: CDCE913

Hi team, 

I would like to cycle VDD/VDDout pin when they drops below recommended range to reset internal registers. 

1. Could you advise the minimum recommended turn off time and minimum voltage for properly achieve reset?

( for example VDD<0.5V, for at least 10ms)

2. Is there a ripple noise requirement on VDD/VDDout pin?

3. Is there a requirement for rise/fall slew rate for VDD/VDDout pin?


  • Hello Tsuji-san,

    We don't normally test this or specify this because of possible external devices - VCXO use. Please advise if customer is using XO, VCXO or LVCMOS input.

    I will talk internally to our team and have and answer for you soon. Please expect and answer by 1/13.

  • Hi Aaron,

    The input is LVCMOS.


  • Hello Tsuji-san,

    Thank you for the additional information.

    1.Minimum turn off time and voltage - voltage level this constraint depends on board capacitance and grounding while turn off time depends on the internal parasitics that we are unable to retrieve at this time.

    2. Ripple noise - best measured as this pertains to the Power Supply Rejection Ratio (PSRR) not easily simulated.

    3. Rise and fall slew rates - the part is not characterized for this specific of a datasheet contraint.

    In short, the datasheet does not characterize these Electrical Characteristics. In order to test for boundaries we would have to try it on the bench and add margin of error but this would be a rough estimate.

    Could I ask what application this is being used for? Are there specific requirements in the use-case that are needed to be met?

  • Hello Tsuji-san,

    I will consider this thread closed as we have not heard back.

    Please feel free to open another thread if needed.