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CDCE72010: Primary and Secondary clock

Part Number: CDCE72010

Dear Team,

Whether primary clock will accept Sine wave??

While we are using Secondary clock as HCMOS what kind of termination required for CDCE72010 


Naveen P

  • Hi Naveen,

    CDCE72010 wasn't really designed to accept single-ended sine wave input, and there are significant restrictions imposed on minimum frequency, signal amplitude, and biasing voltage by trying to use a sine wave input. however, if those restrictions can be satisfied, datasheet rated characteristics should be achievable. Due to the shared register settings for PRI_REF and SEC_REF, and the constraint of HCMOS on the SEC_REF clock, a tradeoff emerges between usable frequency range, signal amplitude, and termination complexity. If you want to see how these restrictions are derived, read on.

    In theory, if your sine wave slew rate is greater than 1V/ns at the minimum VOH and maximum VOL (according to the datasheet for LVCMOS input, VOH = 0.7VCC, VOL = 0.3VCC), you could drive a sine wave on the primary reference while the primary is configured for LVCMOS. Normally an LVCMOS signal is a sharp edge transition from low to high and vice versa, so the slew rate throughout the waveform (and at the limit crossings) can be taken as approximately constant. But with a sine wave, the slew rate depends on the amplitude at which it is measured, which will inevitably impose limitations on the minimum amplitude and frequency.

    Since 0.7VCC and 0.3VCC are symmetric about VCC/2 and the zero-crossing, they will have the same magnitude of slew rate. Moreover, we know that the slew rate of a sine wave characterized by Asin(2πft) + VCC/2 is given by the derivative 2πfAcos(2πft). We can compute the time at which the sine wave achieves either 0.7VCC or 0.3VCC by expressing the voltage in terms of VCC and the sine wave amplitude. 0.7VCC = Asin(2πft) + VCC/2, and thus t = arcsin(VCC / (5A) ) / (2πf). Finally, we can substitute that t value into the derivative expression to determine the required amplitude as a function of VCC and frequency:

    slew rate = 2πf*A*cos(2πf*arcsin(VCC/(5A))/(2πf))

    Rearranging for values we know:

    1V/ns = 2π * Fin * Vpk * cos(arcsin(VCC/(5Vpk)))

    Given a 3.3V supply and assuming the sine wave is somehow biased to VCC/2, the minimum usable sine wave can be computed as:

    Fin = 1V/ns / (2π * 1.65V * cos(arcsin(0.4))) = ~105.25 MHz

    Sine waves of higher frequency will have higher slew rate, and could be used without issue. If the offset changes, this requires a higher slew rate for the farther of the two limits, and also necessitates a lower Vpk to avoid triggering the ESD diodes.

    Note that it is very likely that the LVCMOS input mode would still work with < 1V/ns slew rate, and the functional thresholds for the logic transition from low to high may be more relaxed than the minimum VOH and maximum VOL specifications in the datasheet. However, failing to observe the datasheet specifications could result in device performance outside of the characterized range.

    If you do try to use a sine wave with the primary reference in LVCMOS mode, the termination may be tricky: still apply 1kΩ to GND on primary N pin, but ideally the primary P pin should match the sine wave source impedance (typically 50Ω) to VCC/2. The primary P VCC/2 should be low enough impedance to be considered an AC-ground.

    As a potentially simpler alternative, you could use both primary and secondary as differential AC-coupled signals, and connect the N terminals of both with 0.1µF to GND. The internal termination should be sufficient for biasing both signals if AC-coupled. The sine wave slew rate is simplified to 1V/ns / (2π*Vpk). From the datasheet, in differential mode, Vinp - Vinn < 1.3V, so we'll take 1.3V as Vpk, and we find that the minimum compliant frequency is 122.4MHz (higher than in MOS mode, due to the reduced maximum differential amplitude; the tradeoff is more convenient termination, as no external bias is required). Meanwhile, 3.3V HCMOS would need to be reduced in amplitude by a small amount to remain compliant with the maximum signal swing requirements, which could be accomplished through a resistor divider without much impact to the HCMOS slew rate (2.5V or 1.8V HCMOS, AC-coupled, should work without additional circuitry).


  • Thanks for your Explanation. We are using a primary clock as a sine wave with 104 MHz 10dbm. with this we are getting a proper PLL output.

    One more question, if i isolate the primary and secondary clock of PLL also I am getting some offset signal with same frequency  in PLL output, Is there any internal reference clock is present in CDCE or due VCXO its generating some offset frequency in output.


    Naveen P