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Original question:

LMX2594: Lmx2594 unstable phase noise

LMX2594: Lmx2594 unstable phase noise

shay Barzilay
Prodigy 220 points
Part Number: LMX2594
Other Parts Discussed in Thread: TIDA-01410

Hello

I am using LMX2594

I am using partial assist

1- Is there a certain legality that needs to be maintained before or after  toggle the register 0 for cal ( 002454 to 00245c)? Minimum  time before or after toggle register 0?

2- I am using 2 pll on the same pcb. The both pll trying to lock on the same time .  I noticed that there is a mutual interference between the components which sometimes expressed in degradation at the phase noise.

3-I made a readback from the component and the vco and the cap value was the same . The daciset value was change to : 8c , 90 or 91 hex .

Best Regards

Shay Barzilay

  • 0
    TI__Mastermind 28021 points

    Shay,

    1.  Follow the proper power on sequencing, which says 10 ms after power is applied to let LDOs warm up.  Then after this, you don't need the 10 ms and you can program R0.  After this, when you toggle R0, it activates VCO calbiration.  We have typical calibration times, and also you can simulate the lock time with our PLLatinum SIm tool.  

    2.   Sounds like frequency pulling, but we had a similar issue with our first attempt at the TIDA-01410 reference design.  We got much better results by separating the power supply planes for the pull-up components for each PLL.

    3.  When you readback, the things are rb_VCO_CAPCTRL, rb_VCO_SEL, and rb_VCO_DACISET.  These are what the device actually chooses.  There is also VCO_CAPCTRL which is different than rb_VCO_CAPCTRL.

    Hope this helps.

    Regards,
    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 220 points

    Hello,

    I am using seperate power plane for each pll but the power come from the same regulator.

    I check the voltage on the pll and it stable during the lock time.

    The strange thing about the phenomenon is that the

    Phase  noise sometimes stays high (10dB higher) and in the next pll lock the phase noise will be OK.

    Best Regards

    Shay

  • 0 in reply to shay Barzilay
    TI__Guru** 110830 points

    Hi Shay,

    If only one of the PLLs is operating, will the phase noise be always stable?

    Can you also simplify the debug by operating in integer channel?

  • 0 in reply to Noel Fung
    Prodigy 220 points

    Hello,

    When I am using one pll I didn't see the problem.

    I add 360usec delay between  pll1 and pll2 lock and the problem stay the same.

    I notice that in regular mode  sometimes the problem appears often and sometimes does not appear at all

    I have a Hunch that I have a digital problem.

    Is there a maximum rate for sending all the 113 registers?

    Mybe there is a register that need a delay before or after.

    Now I am sending all the data in 20MHz rate.

    Best Regards

    Shay

  • 0 in reply to shay Barzilay
    TI__Guru** 110830 points

    Hi Shay,

    Does your application require programming the two pll simultaneously?

    If so, can you try set OUT_MUTE = 1, OUT_FORCE = 0?

    Or, can you try set OUTx_PD = 1 during programing and then set it back to = 0 after the pll are locked?

    Both of these trials are trying to reduce the interference by muting the RF output.

  • 0 in reply to Noel Fung
    Prodigy 220 points

    Hello,

    Ok, I will try .

    What about the digital questions from the previous email

    Best Regards

    Shay

  • 0 in reply to shay Barzilay
    TI__Guru** 110830 points

    Hi Shay,

    No, there is no speed limit on this. As long as the SPI CLK rate is less than 75MHz, we can for sure that the registers will get written.

    However, for initial power up programming, we recommend program R0 twice with a wait time of 10ms between the write. This is to ensure that the internal LDOs are up and settled down before calibration.

    See datasheet section 7.5.1 for details.