Hi team,
My customer is considering to use the CDCS503. Could you support the questions below?
1. Is it okay if the SSCG input clock stops then returns?
2. Is it necessary to have a Delay time for the output to be valid after the input clock is supplied?
Regards,
Yamaguchi
Hi Yamaguchi,
A1. Typical application uses clock input without SSC, and applies SSC to the clock output. It is OK if the clock stops, however you will not have an output clock during this time.
A2. Unfortunately I did not locate the data on delay time. However you may be interested in this thread: 
In this thread, you can see a plot of the output behavior when SSC_SEL1 changes to enable SSC while the clock is available. As you can see, there SSC output is always stable with low delay time
Kind regards,
Lane
